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公开(公告)号：US20180177040A1
公开(公告)日：2018-06-21
申请号：US15840598
申请日：2017-12-13
Applicant: Onkyo Corporation
Inventor： Makoto YOSHIDA
CPC classification number: H05K1/115 , H05K1/0215 , H05K1/0216 , H05K1/0225 , H05K1/0259 , H05K9/0039 , H05K9/006 , H05K2201/093 , H05K2201/09327 , H05K2201/09354
Abstract: A multilayer substrate includes plural layers of circuit patterns. Each circuit pattern includes a ground conductor surrounding a wiring region provided with a conductive wiring pattern. Each ground conductor includes a slit connecting between the outside of the multilayer substrate and the wiring region. In the multilayer substrate, the slit of the ground conductor provided at one of adjacent two layers of the circuit patterns and the slit of the ground conductor provided at the other circuit pattern are formed at positions not overlapping with each other. That is, these slits are formed at such positions that a view in an upper-to-lower direction is blocked. The shape of the slit of each ground conductor is in such a shape that a view from an end side of the multilayer substrate to a wiring region side is blocked.
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82.发明授权Metal electromagnetic interference (EMI) shielding coating along an edge of a ceramic substrate 有权沿陶瓷基片边缘的金属电磁干扰（EMI）屏蔽涂层公开(公告)号：US09583445B2
公开(公告)日：2017-02-28
申请号：US14218384
申请日：2014-03-18
Applicant: Apple Inc.
Inventor： Richard H. Dinh , Ashutosh Y. Shukla , Scott A. Myers
IPC: H01L23/552 , H01L27/146 , H01L23/498 , H05K1/02 , H05K1/18 , H01L23/13 , H01L23/15 , H01L23/00 , H05K3/00 , H05K3/36
CPC classification number: H01L23/552 , H01L23/13 , H01L23/15 , H01L23/49805 , H01L23/49827 , H01L23/49838 , H01L24/13 , H01L24/16 , H01L24/81 , H01L27/14618 , H01L2224/0401 , H01L2224/131 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/81801 , H01L2924/12041 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15151 , H01L2924/15159 , H01L2924/15162 , H01L2924/15311 , H01L2924/15787 , H05K1/0218 , H05K1/189 , H05K3/0052 , H05K3/363 , H05K2201/053 , H05K2201/056 , H05K2201/09145 , H05K2201/09354 , H05K2201/09509 , H05K2201/09618 , H05K2201/10378 , H05K2201/2018 , H01L2924/014 , H01L2924/00
Abstract: An electrical component may be mounted on a substrate such as a ceramic substrate. Contacts may be formed on upper and lower surfaces of the substrate. The electrical component may be soldered to the contacts on the upper surface. The contacts on the lower surface may be used to solder the substrate to a printed circuit. During manufacturing, it may be desirable to use metal traces on a ceramic panel to make connections to contacts on the substrate. Following singulation of the ceramic panel to form the ceramic substrate, some of the metal traces may run to the edge of the ceramic substrate. A folded tab of the printed circuit may form a shield that covers these exposed traces. A divided metal-coated groove or a row of divided metal-coated vias running along each edge of the substrate may also provide shielding.
Abstract translation: 电气部件可以安装在诸如陶瓷基板的基板上。 可以在基板的上表面和下表面上形成接触。 电气部件可以焊接到上表面上的触点。 下表面上的触点可用于将基板焊接到印刷电路。 在制造过程中，可能需要在陶瓷板上使用金属迹线来连接到基板上的触点。 在陶瓷面板分层以形成陶瓷衬底之后，一些金属迹线可以流到陶瓷衬底的边缘。 印刷电路的折叠片可以形成覆盖这些暴露痕迹的屏蔽。 沿着衬底的每个边缘延伸的划分的金属涂覆的凹槽或一排划分的金属涂覆的通孔也可以提供屏蔽。
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公开(公告)号：US09370092B2
公开(公告)日：2016-06-14
申请号：US14490698
申请日：2014-09-19
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Hiromichi Kitajima
CPC classification number: H05K1/0224 , H05K1/0219 , H05K1/0298 , H05K1/115 , H05K1/117 , H05K3/3457 , H05K2201/0715 , H05K2201/09354 , H05K2201/09663 , H05K2201/099
Abstract: A multilayer wiring board including a multilayer body including a plurality of insulating layers includes a ground electrode for external connection disposed in a center of a lower surface of the multilayer body, a plurality of individual electrodes at an outer edge of the lower surface of the multilayer body, and a surface insulating film including an interelectrode insulating portion and a surface covering portion, the interelectrode insulating portion covering an edge portion of the ground electrode to provide insulation between the ground electrode and each of the individual electrodes, the surface covering portion being disposed on a surface of a main body of the ground electrode to divide the surface of the main body into a plurality of regions.
Abstract translation: 包括具有多个绝缘层的多层体的多层布线基板包括设置在多层体的下表面的中心的外部连接用接地电极，多层单体的下表面外缘的多个单独电极 主体和包括电极间绝缘部分和表面覆盖部分的表面绝缘膜，所述电极间绝缘部分覆盖所述接地电极的边缘部分，以在所述接地电极和每个所述各个电极之间提供绝缘，所述表面覆盖部分被布置 在接地电极的主体的表面上，将主体的表面分割成多个区域。
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公开(公告)号：US20150263694A1
公开(公告)日：2015-09-17
申请号：US14637040
申请日：2015-03-03
Applicant: LSIS CO., LTD.
Inventor： Jong In SUN
CPC classification number: H05K1/18 , B60L53/14 , H03H7/427 , H05K1/0215 , H05K1/0231 , H05K1/0233 , H05K1/0234 , H05K2201/09354
Abstract: A printed circuit board (PCB) for reducing EMI of an electric vehicle is provided. The PCB includes an electromagnetic interference (EMI) filter connected to a battery power supply and filtering EMI noise, a plurality of chassis ground (GND) terminals, a chassis GND pattern formed to ground a power GND terminal to the plurality of chassis GND terminals, a coupling prevention capacitor installed between the power GND terminal and the plurality of chassis GND terminals to prevent noise coupling between the power GND terminal and the chassis GND terminals, and a merge resistor installed between the power GND terminal and the plurality of chassis GND terminals to merge noise occurring when charging the battery power supply to the plurality of chassis GND terminals.
Abstract translation: 提供了用于降低电动车辆的EMI的印刷电路板（PCB）。 PCB包括连接到电池电源和滤除EMI噪声的电磁干扰（EMI）滤波器，多个机壳接地（GND）端子，形成为将电源GND端子接地到多个机架GND端子的机架GND图案， 电源GND端子和多个机架GND端子之间设置耦合防止电容器，以防止电源GND端子和机架GND端子之间的噪声耦合;以及合并电阻器，其安装在电源GND端子和多个机架GND端子之间， 将电池电源充电到多个机箱GND端子时发生合并噪声。
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公开(公告)号：US20150221600A1
公开(公告)日：2015-08-06
申请号：US14686922
申请日：2015-04-15
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yuki WAKABAYASHI
CPC classification number: H01L23/66 , H01L23/49822 , H01L23/5384 , H01L25/165 , H01L2223/6616 , H01L2223/6655 , H01L2223/6677 , H01L2224/16225 , H01L2924/1421 , H01L2924/15313 , H01L2924/19105 , H01L2924/3025 , H04B5/0056 , H05K1/0218 , H05K1/0243 , H05K1/0298 , H05K1/11 , H05K1/181 , H05K2201/09354 , H05K2201/09618
Abstract: A high-frequency module includes a laminate, a bottom surface electrode, and internal electrodes that provide grounding. The bottom surface electrode is provided on a bottom surface of the laminate. The laminate includes a wiring region through which wiring of a high-frequency circuit passes. The internal electrodes that provide grounding are provided between layers of the laminate and connected to the bottom surface electrode, respectively. The internal electrodes that provide grounding each include a line including ends extending outside of the wiring region along an outer edge of the laminate. The internal electrodes that provide grounding are endlessly continuous with each other when seen in a lamination direction of the laminate.
Abstract translation: 高频模块包括层叠体，底面电极和提供接地的内部电极。 底面电极设置在层叠体的底面上。 层叠体包括高频电路的布线通过的布线区域。 提供接地的内部电极分别设置在层压体的层之间并分别连接到底面电极。 提供接地的内部电极包括沿着层压体的外边缘延伸到布线区域外侧的端部的线。 当层叠体的层叠方向观察时，提供接地的内部电极彼此连续地连续。
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Patent Agency Ranking
公开(公告)号：US20150216034A1
公开(公告)日：2015-07-30
申请号：US14490698
申请日：2014-09-19
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Hiromichi KITAJIMA
CPC classification number: H05K1/0224 , H05K1/0219 , H05K1/0298 , H05K1/115 , H05K1/117 , H05K3/3457 , H05K2201/0715 , H05K2201/09354 , H05K2201/09663 , H05K2201/099
Abstract: A multilayer wiring board including a multilayer body including a plurality of insulating layers includes a ground electrode for external connection disposed in a center of a lower surface of the multilayer body, a plurality of individual electrodes at an outer edge of the lower surface of the multilayer body, and a surface insulating film including an interelectrode insulating portion and a surface covering portion, the interelectrode insulating portion covering an edge portion of the ground electrode to provide insulation between the ground electrode and each of the individual electrodes, the surface covering portion being disposed on a surface of a main body of the ground electrode to divide the surface of the main body into a plurality of regions.
Abstract translation: 包括具有多个绝缘层的多层体的多层布线基板包括设置在多层体的下表面的中心的外部连接用接地电极，多层单体的下表面外缘的多个单独电极 主体和包括电极间绝缘部分和表面覆盖部分的表面绝缘膜，所述电极间绝缘部分覆盖所述接地电极的边缘部分，以在所述接地电极和每个所述各个电极之间提供绝缘，所述表面覆盖部分被布置 在接地电极的主体的表面上，将主体的表面分割成多个区域。
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87.发明授权Wireless terminal with reduced specific absorption rate peak and implementation method thereof 有权具有降低比吸收率峰值的无线终端及其实施方法公开(公告)号：US09095052B2
公开(公告)日：2015-07-28
申请号：US13520908
申请日：2010-07-19
Applicant: Lu Zhang
Inventor： Lu Zhang
CPC classification number: H05K1/02 , H05K1/0224 , H05K1/0298 , H05K3/00 , H05K2201/09145 , H05K2201/09354 , Y10T29/49124
Abstract: The disclosure discloses a wireless terminal with a reduced Specific Absorption Rate (SAR) peak. The wireless terminal comprises a Printed Circuit Board (PCB), wherein a fractal gap is formed at an edge of a metal ground on the PCB to disturb distribution of induced current at the edge of the metal ground. The disclosure also discloses a method for reducing an SAR peak. On the premise of the non-influence on the communication quality of the wireless terminal, the SAR and the production cost can be reduced and the structure space of wireless terminal can be saved by using the wireless terminal and the method.
Abstract translation: 本公开公开了一种具有降低的比吸收率（SAR）峰值的无线终端。 无线终端包括印刷电路板（PCB），其中在PCB上的金属接地的边缘处形成分形间隙以干扰金属接地边缘处的感应电流的分布。 本公开还公开了一种降低SAR峰的方法。 在不影响无线终端通信质量的前提下，可以减少SAR和生产成本，通过无线终端和方法可以节省无线终端的结构空间。
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88.发明申请PRINTED CIRCUIT BOARD OF SEMICONDUCTOR PACKAGE FOR DECREASING NOISE BY ELECTROMAGNETIC INTERFERENCE 审中-公开印刷电路板用于通过电磁干扰减少噪音的半导体封装公开(公告)号：US20130319731A1
公开(公告)日：2013-12-05
申请号：US13846342
申请日：2013-03-18
Inventor： Yun Im Lee
IPC: H05K1/02
CPC classification number: H05K1/0216 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/552 , H01L23/66 , H01L24/48 , H01L2223/6616 , H01L2224/48227 , H01L2924/00014 , H01L2924/142 , H01L2924/1435 , H01L2924/15192 , H01L2924/15311 , H05K1/0219 , H05K2201/09354 , H05K2201/09618 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A printed circuit board for a semiconductor package which is capable of reducing noise by electromagnetic interference (EMI), including: an upper circuit layer in which a first circuit pattern is formed; an intermediate circuit layer that is disposed below the upper circuit layer and has a second circuit pattern formed therein; a lower circuit layer that is disposed below the intermediate circuit layer and has a third circuit pattern formed therein; an insulating layer disposed between the first and second circuit patterns and between the second and third circuit patterns; vias that vertically connect the first, second and third circuit patterns; and EMI blocking vias that are arranged along edge portions of the first, second and third circuit patterns and are connected to a ground layer.
Abstract translation: 一种用于半导体封装的印刷电路板，其能够通过电磁干扰（EMI）降低噪声，包括：形成第一电路图案的上电路层; 中间电路层，其设置在所述上电路层的下方，并且形成有第二电路图案; 下电路层，其设置在所述中间电路层的下方，并且具有形成在其中的第三电路图案; 设置在第一和第二电路图案之间以及第二和第三电路图案之间的绝缘层; 垂直连接第一，第二和第三电路图案的通孔; 以及沿着第一，第二和第三电路图案的边缘部分布置并连接到接地层的EMI阻挡通孔。
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89.发明申请WIRELESS TERMINAL WITH REDUCED SPECIFIC ABSORPTION RATE PEAK AND IMPLEMENTATION METHOD THEREOF 有权具有降低特定吸收率峰值的无线终端及其实现方法公开(公告)号：US20130118780A1
公开(公告)日：2013-05-16
申请号：US13520908
申请日：2010-07-19
Applicant: Lu Zhang
Inventor： Lu Zhang
CPC classification number: H05K1/02 , H05K1/0224 , H05K1/0298 , H05K3/00 , H05K2201/09145 , H05K2201/09354 , Y10T29/49124
Abstract: The disclosure discloses a wireless terminal with a reduced Specific Absorption Rate (SAR) peak. The wireless terminal comprises a Printed Circuit Board (PCB), wherein a fractal gap is formed at an edge of a metal ground on the PCB to disturb distribution of induced current at the edge of the metal ground. The disclosure also discloses a method for reducing an SAR peak. On the premise of the non-influence on the communication quality of the wireless terminal, the SAR and the production cost can be reduced and the structure space of wireless terminal can be saved by using the wireless terminal and the method.
Abstract translation: 本公开公开了一种具有降低的比吸收率（SAR）峰值的无线终端。 无线终端包括印刷电路板（PCB），其中在PCB上的金属接地的边缘处形成分形间隙以干扰金属接地边缘处的感应电流的分布。 本公开还公开了一种降低SAR峰的方法。 在不影响无线终端通信质量的前提下，可以减少SAR和生产成本，通过无线终端和方法可以节省无线终端的结构空间。
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公开(公告)号：US20130092429A1
公开(公告)日：2013-04-18
申请号：US13644092
申请日：2012-10-03
Applicant: Jason John Ellison
Inventor： Jason John Ellison
CPC classification number: H05K1/117 , H01R12/523 , H01R13/6471 , H05K1/0218 , H05K1/0219 , H05K1/0245 , H05K2201/09154 , H05K2201/09354 , H05K2201/09618 , H05K2201/09781
Abstract: An electrical connector includes a printed circuit board that includes a body that carries a plurality of ground conductors that define respective ground contact pads, and a plurality of signal conductors that define respective signal contact pads. The contact pads are configured to mate with electrical contacts of a complementary electrical connector. The printed circuit board includes a ground coupling assembly that electrically connects at least a pair of the ground conductors.
Abstract translation: 电连接器包括印刷电路板，其包括承载限定各个接地焊盘的多个接地导体的本体，以及限定相应的信号接触焊盘的多个信号导体。 接触垫被配置成与互补的电连接器的电触点配合。 印刷电路板包括电连接至少一对接地导体的接地耦合组件。
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