公开(公告)号：US20170309556A1

公开(公告)日：2017-10-26

申请号：US15523478

申请日：2015-11-20

Applicant: NSK Ltd.

Inventor： Shigeru SHIMAKAWA ,  Takashi SUNAGA ,  Takaaki SEKINE ,  Teruyoshi KOGURE ,  Ryoichi SUZUKI

IPC: H01L23/495 ,  H01L49/02

CPC classification number: H01L23/49568 ,  B62D5/0406 ,  G01R1/203 ,  H01L23/12 ,  H01L23/36 ,  H01L23/48 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49537 ,  H01L23/49558 ,  H01L23/49861 ,  H01L23/50 ,  H01L24/34 ,  H01L24/37 ,  H01L25/071 ,  H01L28/20 ,  H01L2224/34 ,  H01L2224/37147 ,  H01L2224/37599 ,  H02K11/33 ,  H05K1/181 ,  H05K3/202 ,  H05K2201/09881 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An electronic heat-dissipating substrate including: lead frames of wiring pattern shapes on a conductor plate; and an insulating member between the lead frames. A plate surface of the lead frames and a top surface of the insulating member form one continuous surface. The part arrangement surface is on both surfaces of the electronic part mounting heat-dissipating substrate, a reductant circuit which includes at least similar dual-system circuit is formed on the electronic part mounting heat-dissipating substrate, a first-system circuit of the dual-system circuit is formed on a first surface of the electronic part mounting heat-dissipating substrate, a second-system circuit of the dual-system circuit is formed on a second surface of the electronic part mounting heat-dissipating substrate, and the common lead frames used in a portion of a circuit wiring are used to the first surface and the second surface of the electronic part mounting heat-dissipating substrate.

公开(公告)号：US09392684B2

公开(公告)日：2016-07-12

申请号：US13833047

申请日：2013-03-15

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Akio Horiuchi

IPC: H05K1/02 ,  H05K3/46 ,  H01L23/498 ,  H01L21/48 ,  H05K3/00 ,  H01L23/14 ,  H01L23/15

CPC classification number: H05K1/0271 ,  H01L21/486 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2224/16 ,  H01L2224/73204 ,  H05K1/0298 ,  H05K3/0055 ,  H05K3/4644 ,  H05K3/4673 ,  H05K2201/09781 ,  H05K2201/09881 ,  Y10T29/49128

Abstract: A method for manufacturing a wiring substrate includes alternately stacking first wiring patterns and first insulative layers on a first surface of a core substrate and alternately stacking second wiring patterns and second insulative layers on a second surface of the core substrate at an opposite side of the first surface. The number of the second insulative layers excluding the outermost second insulative layer differs from the number of the first insulative layers. The method further includes forming a via hole in the outermost first insulative layer to expose a portion of the outermost first wiring pattern, and exposing the outermost second wiring pattern by reducing the outermost second insulative layer in thickness. The method further includes forming a via in the via hole and forming a wiring pattern, which is connected by the via to the outermost first wiring pattern, on the outermost first insulative layer.

Abstract translation: 制造布线基板的方法包括：在芯基板的第一表面上交替地堆叠第一布线图案和第一绝缘层，并且在芯基板的第二表面上交替地堆叠第二布线图案和第二绝缘层， 表面。 除了最外侧的第二绝缘层以外的第二绝缘层的数量与第一绝缘层的数量不同。 该方法还包括在最外部第一绝缘层中形成通孔以暴露最外面的第一布线图案的一部分，以及通过减小最外层第二绝缘层的厚度来露出最外面的第二布线图案。 该方法还包括在通孔中形成通孔，并且在最外的第一绝缘层上形成通过通孔连接到最外面的第一布线图案的布线图案。

公开(公告)号：US20150351229A1

公开(公告)日：2015-12-03

申请号：US14289098

申请日：2014-05-28

Applicant: Avago Technologies General IP (Singapore) Pte. Ltd

Inventor： Lea-Teng Lee ,  Sarah Haney

IPC: H05K1/02 ,  H05K3/06 ,  H05K1/09

CPC classification number: H05K1/0268 ,  H05K2201/09881 ,  H05K2201/09909 ,  H05K2203/0353 ,  H05K2203/0588

Abstract: A printed circuit board (PCB) comprises a non-conductive base layer, a conductive interconnect disposed on the non-conductive base layer and comprising at least two surface pads separated by a trench, and a insulating dam disposed in the trench, wherein the insulating dam electrically isolates the at least two surface pads and has an upper surface that is substantially co-planar with respective upper surfaces of the at least two surface pads.

Abstract translation: 印刷电路板（PCB）包括非导电基底层，布置在非导电基底层上的导电互连，并且包括由沟槽分隔开的至少两个表面焊盘和设置在沟槽中的绝缘堤坝，其中绝缘 坝至少两个表面焊盘电隔离，并且具有与至少两个表面焊盘的相应上表面基本共面的上表面。

公开(公告)号：US20150177621A1

公开(公告)日：2015-06-25

申请号：US14634527

申请日：2015-02-27

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jeong Woo LEE ,  Going Sik Kim

IPC: G03F7/30 ,  H05K3/46

CPC classification number: G03F7/30 ,  G03F7/095 ,  G03F7/2022 ,  G03F7/2024 ,  H05K1/0284 ,  H05K3/28 ,  H05K3/4673 ,  H05K2201/0195 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0588 ,  H05K2203/1476

Abstract: Disclosed herein is a printed circuit board, including: a base substrate on which a circuit layer is formed; and multi-layer insulating layers formed in a plurality of layers on the base substrate, including the circuit layer, each of the plurality of layers being formed to have a step structure, wherein the multi-layer insulating layer is formed of heterogeneous materials.

Abstract translation: 这里公开了一种印刷电路板，包括：基底，其上形成有电路层; 以及在所述基底基板上形成为多层的多层绝缘层，所述多层绝缘层包括所述电路层，所述多层中的每一层形成为具有台阶结构，其中所述多层绝缘层由异质材料形成。

公开(公告)号：US20150062915A1

公开(公告)日：2015-03-05

申请号：US14019257

申请日：2013-09-05

Applicant: Cree, Inc.

Inventor： Christopher P. Hussell ,  Jesse Colin Reiherzer ,  Erin R. F. Welch ,  Florin A. Tudorica

IPC: H01L33/10 ,  F21K99/00 ,  F21V7/22

CPC classification number: F21V7/22 ,  F21K9/60 ,  H01L25/0753 ,  H01L33/60 ,  H01L33/62 ,  H01L2924/0002 ,  H05K1/0274 ,  H05K3/28 ,  H05K2201/09881 ,  H05K2201/10106 ,  H05K2201/2054 ,  H05K2203/0588 ,  H01L2924/00

Abstract: Light emitter devices and methods are provided herein. In some aspects, emitter devices and methods provided herein are for light emitting diode (LED) chips and can include providing a substrate, a conductive trace over the substrate, and at least one or more direct attach LED chip over the substrate. A layer of non-conductive and reflective material is disposed over the surface of wherein the layer of reflective material covers at least 25% or more of a surface of the substrate.

Abstract translation: 本文提供了发光器件和方法。 在一些方面，本文提供的发射器件和方法用于发光二极管（LED）芯片，并且可以包括提供衬底，衬底上的导电迹线以及衬底上的至少一个或多个直接附接LED芯片。 非导电和反射材料层设置在其上的反射材料层覆盖基底表面的至少25％或更多的表面上。

公开(公告)号：US08835773B2

公开(公告)日：2014-09-16

申请号：US12752692

申请日：2010-04-01

Applicant: Shigetsugu Muramatsu ,  Yasuhiko Kusama

Inventor： Shigetsugu Muramatsu ,  Yasuhiko Kusama

IPC: H05K1/16 ,  H05K7/00 ,  H05K3/34 ,  H01L23/498 ,  H01L21/56 ,  H05K3/00 ,  H01L23/31 ,  H05K3/30 ,  H05K1/11 ,  H05K3/24

CPC classification number: H05K3/3452 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15151 ,  H05K1/111 ,  H05K3/0044 ,  H05K3/243 ,  H05K3/305 ,  H05K2201/0191 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/025 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method of manufacturing a wiring board for use in mounting of an electronic component includes: forming an outermost wiring layer on a surface side where the electronic component is mounted; forming an insulating layer so as to cover the wiring layer; and forming a concave portion in the insulating layer. The concave portion is formed by removing, using a mask formed in a required shape by patterning, an exposed portion of the insulating layer in a step-like shape until a surface of a pad defined at a portion of the wiring layer is exposed. The concave portion is preferably formed by removing the portion of the insulating layer by sand blast.

Abstract translation: 制造电子部件安装用布线基板的方法包括：在安装有电子部件的表面侧形成最外层布线层; 形成绝缘层以覆盖所述布线层; 以及在所述绝缘层中形成凹部。 通过使用通过图案化形成所需形状的掩模，以阶梯状形状除去绝缘层的露出部分，直到露出布线层的一部分的焊盘的表面来形成凹部。 凹部优选通过用喷砂除去绝缘层的一部分而形成。

公开(公告)号：US20140226346A1

公开(公告)日：2014-08-14

申请号：US14177599

申请日：2014-02-11

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kazutaka KOBAYASHI ,  Mitsuhiro AIZAWA ,  Hiroshi SHIMIZU ,  Mina IWAI

IPC: F21V19/00 ,  H05K1/02

CPC classification number: H05K1/0274 ,  H01L24/45 ,  H01L25/0753 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K3/007 ,  H05K3/06 ,  H05K3/187 ,  H05K3/243 ,  H05K3/26 ,  H05K3/285 ,  H05K3/287 ,  H05K3/303 ,  H05K2201/0162 ,  H05K2201/09881 ,  H05K2201/10106 ,  H05K2201/10553 ,  H05K2201/2054 ,  H05K2203/0126 ,  H05K2203/0191 ,  H05K2203/0285 ,  H05K2203/0369 ,  H05K2203/075 ,  H05K2203/087 ,  H05K2203/095 ,  H05K2203/107 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: There is provided a wiring board. The wiring board includes: a first insulating layer; a plurality of wiring patterns on the first insulating layer so as to be spaced apart from each other; a plating layer on at least one of the wiring patterns; a second insulating layer containing silicone therein and having an opening, wherein an outermost surface of the plating layer is exposed from the opening and serves as a connection pad; and a silica film on the outermost surface of the plating layer.

Abstract translation: 提供了一个接线板。 布线板包括：第一绝缘层; 在所述第一绝缘层上的多个布线图案彼此间隔开; 至少一个布线图案上的镀层; 第二绝缘层，其中含有硅酮并具有开口，其中所述镀层的最外表面从所述开口暴露并用作连接垫; 以及在镀层的最外表面上的二氧化硅膜。

公开(公告)号：US08586871B2

公开(公告)日：2013-11-19

申请号：US13185866

申请日：2011-07-19

Applicant: Jonathan J. Bernstein ,  Brian R. Smith ,  Thomas E. Boydston

Inventor： Jonathan J. Bernstein ,  Brian R. Smith ,  Thomas E. Boydston

IPC: H05K1/09

CPC classification number: H05K1/0275 ,  H05K3/125 ,  H05K2201/0224 ,  H05K2201/09881 ,  H05K2203/013

Abstract: An interconnect scheme includes a conductive ink forming a plurality of conductive regions, and a dielectric ink occupying spaces between the conductive regions. The conductive ink and the dielectric ink have substantially identical optical, acoustic, and x-ray absorption properties, thereby making the interconnect scheme tamper-resistant and/or difficult to identify and reverse-engineer using conventional detection methods.

Abstract translation: 互连方案包括形成多个导电区域的导电油墨和占据导电区域之间的空间的电介质油墨。 导电油墨和电介质油墨具有基本上相同的光学，声学和x射线吸收特性，从而使得互连方案具有防篡改和/或难以使用常规检测方法进行识别和反向工程。

公开(公告)号：US20130292166A1

公开(公告)日：2013-11-07

申请号：US13930733

申请日：2013-06-28

Applicant: IBIDEN CO., LTD.

Inventor： Masaru Takada ,  Fusaji Nagaya ,  Takao Okada ,  Tomohiko Murata

IPC: H05K1/11

CPC classification number: H05K1/111 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81385 ,  H01L2224/85411 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K3/244 ,  H05K3/28 ,  H05K3/3452 ,  H05K2201/09481 ,  H05K2201/09881 ,  H05K2201/10674 ,  H05K2203/049 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A printed wiring board includes a resin layer, pads formed on the resin layer and positioned to be connected to an electronic component, and a solder-resist layer formed on the resin layer and exposing upper surfaces of the pads and portions of side walls of the pads. Each of the pads has a metal layer such that the metal layer is formed on each of the upper surfaces of the pads and each of the portions of the side walls of the pads exposed by the solder-resist layer.

Abstract translation: 印刷电路板包括：树脂层，形成在树脂层上并定位成连接到电子部件的焊盘和形成在树脂层上的阻焊层，并暴露焊盘的上表面和侧壁的部分 垫 每个焊盘具有金属层，使得金属层形成在焊盘的每个上表面上，并且由焊料抗蚀剂层暴露的焊盘的侧壁的每个部分。

公开(公告)号：US08426747B2

公开(公告)日：2013-04-23

申请号：US12923773

申请日：2010-10-07

Applicant: Shinya Uchibori ,  Nobumasa Handa ,  Yuuki Sanada

Inventor： Shinya Uchibori ,  Nobumasa Handa ,  Yuuki Sanada

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K3/4644 ,  H05K1/0265 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/025 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: In a printed wiring board, a first inner layer wiring line is formed on one surface of a wiring line formation layer, a resin film made of electric insulation resin is formed on an area other than the first inner layer wiring line formed on the wiring line formation layer. The resin film and the first inner layer wiring line have the same plane surface. A second wiring line is formed on the resin film, and the second wiring line is thinner in thickness than the first inner layer wiring line. A limit of error in thickness of the resin film and the first inner layer wiring line is within 10% of the thickness of each of the resin film and the first inner layer wiring line.

Abstract translation: 在印刷布线板中，在布线线形成层的一个表面上形成第一内层布线，在布线上形成的除了第一内层布线以外的区域形成由电绝缘树脂构成的树脂膜 形成层。 树脂膜和第一内层布线具有相同的平面。 在树脂膜上形成第二布线，第二布线比第一内层布线更薄。 树脂膜和第一内层布线的厚度误差在树脂膜和第一内层布线的厚度的10％以内。