公开(公告)号：US09603237B2

公开(公告)日：2017-03-21

申请号：US14424831

申请日：2013-08-06

Applicant: Robert Bosch GmbH

Inventor： Tobias Stiefel

IPC: H05K1/02

CPC classification number: H05K1/0259 ,  H02K11/26 ,  H05K2201/10204

Abstract: Surge arrester for a an electric machine, comprising a dummy component (2) which is, compared to components on a circuit board (1) of the electric machine, mounted at the shortest distance from a discharge element (4) of the electric machine, the dummy component (2) being connected to earth potential in at least one terminal.

公开(公告)号：US20170077023A1

公开(公告)日：2017-03-16

申请号：US15364143

申请日：2016-11-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H05K1/11 ,  H01L21/48 ,  H05K1/18

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer.

Abstract translation: 半导体衬底包括：1）具有第一表面和与第一表面相对的第二表面的第一电介质结构; 2）具有与第三表面相对的第三表面和第四表面的第二介电结构，其中第四表面面向第一表面，第二介电结构限定从第三表面延伸到第四表面的通孔，其中腔是 由通孔和第一电介质结构限定; 3）设置在第一介电结构的第一表面上的第一图案化导电层; 以及4）第二图案化导电层，设置在所述第一介电结构的第二表面上并且包括至少一个导电迹线。 第一介电结构限定至少一个开口以暴露第二图案化导电层的一部分。

公开(公告)号：US09585256B2

公开(公告)日：2017-02-28

申请号：US14565532

申请日：2014-12-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Naoki Gouchi

IPC: H05K1/18 ,  H05K3/46 ,  B32B37/18 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H01L23/00 ,  B32B37/04 ,  B32B37/14 ,  H05K7/10 ,  H05K7/12

CPC classification number: H05K1/185 ,  B32B37/04 ,  B32B37/142 ,  B32B37/18 ,  B32B2305/342 ,  H01L24/19 ,  H01L24/25 ,  H01L2224/04105 ,  H01L2224/2518 ,  H01L2924/12042 ,  H05K1/0298 ,  H05K1/0313 ,  H05K1/115 ,  H05K1/181 ,  H05K1/186 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/0141 ,  H05K2201/0154 ,  H05K2201/09781 ,  H05K2201/10 ,  H05K2201/1006 ,  H05K2201/10204 ,  H05K2203/063 ,  H01L2924/00

Abstract: A component-embedded substrate includes a multilayer body formed by stacking up a plurality of resin layers in a predetermined direction, a component embedded in the multilayer body, the component having a plurality of terminal electrodes, a plurality of joining conductors provided in the multilayer body and joined to the plurality of terminal electrodes, a plurality of wiring conductors provided in the multilayer body and electrically coupled to the plurality of joining conductors and at least one auxiliary member enclosed within an outer boundary of the component provided in the multilayer body. The auxiliary member may be electrically insulated from each of the plurality of wiring conductors and arranged to balance pressures acting on the plurality of terminal electrodes when pressure is applied on the multilayer body.

Abstract translation: 部件嵌入式基板包括通过沿预定方向堆叠多个树脂层而形成的多层体，嵌入在多层体中的部件，具有多个端子电极的部件，设置在多层体中的多个接合导体 并且与所述多个端子电极接合，设置在所述多层体中并电耦合到所述多个接合导体的多个布线导体和包围在设置在所述多层体中的所述部件的外边界内的至少一个辅助构件。 辅助构件可以与多个布线导体中的每一个电绝缘，并且被布置为当在多层体上施加压力时平衡作用在多个端子电极上的压力。

公开(公告)号：US09304636B2

公开(公告)日：2016-04-05

申请号：US14032213

申请日：2013-09-20

Applicant: Mitchell Stewart Burberry ,  Ronald Steven Cok ,  Roger G. Markham

Inventor： Mitchell Stewart Burberry ,  Ronald Steven Cok ,  Roger G. Markham

IPC: G06F3/044 ,  G06F3/046 ,  G06F1/16 ,  G06F3/041 ,  G06F3/042 ,  H05K1/02 ,  G06F3/047

CPC classification number: G06F3/044 ,  G06F1/16 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/042 ,  G06F3/046 ,  G06F3/047 ,  G06F2203/04103 ,  G06F2203/04107 ,  G06F2203/04111 ,  G06F2203/04112 ,  H05K1/0216 ,  H05K1/0296 ,  H05K2201/10204 ,  Y10T29/49105 ,  Y10T29/49117

Abstract: A touch-screen device is disclosed having a touch-sensitive area that includes a plurality of patterned driver electrodes, each having a plurality of patterned conductive electrically connected driver micro-wires. An unpatterned conductive layer that is unpatterned in the touch-sensitive area is in electrical contact with the driver micro-wires of the driver electrodes. A plurality of patterned sensor electrodes each includes a plurality of patterned conductive electrically connected sensor micro-wires. A dielectric layer is located between the driver electrodes and the sensor electrodes.

Abstract translation: 公开了一种具有触敏区域的触摸屏设备，该触敏区域包括多个图案化的驱动器电极，每个具有多个图案化的导电电连接的驱动器微线。 在感应区域中未图案化的未图案化的导电层与驱动电极的驱动器微线电接触。 多个图案化传感器电极各自包括多个图案化的导电电连接的传感器微线。 电介质层位于驱动电极和传感器电极之间。

公开(公告)号：US20160087175A1

公开(公告)日：2016-03-24

申请号：US14581474

申请日：2014-12-23

Applicant: LG Display Co., Ltd.

Inventor： Dong Hun Lee

IPC: H01L33/62 ,  H05K1/18 ,  F21V8/00 ,  F21V23/00

CPC classification number: H01L33/62 ,  G02B6/0068 ,  G02B6/0073 ,  G02B6/0083 ,  H01L33/486 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H05K1/181 ,  H05K2201/09781 ,  H05K2201/10106 ,  H05K2201/10136 ,  H05K2201/10204 ,  Y02P70/611 ,  H01L2924/00014

Abstract: Disclosed is a light emitting diode (LED) package, which can be used for, for example, a light source module, a backlight unit and a display device, that may, for example, include an LED chip in a body portion of the LED package; first and second lead frames separated from each other in the body portion, each of the first and second lead frames including first and second leads that are electrically connected to the LED chip and are used as one of anode and cathode leads; and first and second dummy lead frames separated from each other in the body portion and electrically insulated from the first and second lead frames.

Abstract translation: 公开了一种发光二极管（LED）封装，其可以用于例如光源模块，背光单元和显示装置，其可以例如在LED的主体部分中包括LED芯片 包; 第一引线框架和第二引线框架在主体部分中彼此分离，第一引线框架和第二引线框架中的每一个包括电连接到LED芯片的第一引线和第二引线，并且用作阳极引线和阴极引线之一; 以及在主体部分彼此分离并与第一和第二引线框架电绝缘的第一和第二虚拟引线框架。

公开(公告)号：US09205698B2

公开(公告)日：2015-12-08

申请号：US14481572

申请日：2014-09-09

Applicant: ASAHI GLASS COMPANY, LIMITED

Inventor： Kohei Horiuchi

IPC: B44C1/22

CPC classification number: B44C1/228 ,  B23K26/382 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/50 ,  B23K2103/54 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/0029 ,  H05K2201/09836 ,  H05K2201/10204 ,  H05K2203/163 ,  H01L2924/00

Abstract: A method including a) forming a through-hole in a dummy substrate including a surface by radiating a laser to the surface of the dummy substrate in a state where the dummy substrate is moved relative to the laser along a direction parallel to the surface of the dummy substrate, b) determining an angle α (−90°

Abstract translation: 一种方法，包括：在虚拟衬底相对于激光器沿着平行于所述虚拟衬底的表面的方向相对于激光器移动的状态下，通过在所述虚设衬底的表面辐射激光而在包括表面的虚设衬底中形成通孔 虚拟基板，b）确定通孔相对于垂直于虚设基板的表面的线的角度α（-90°<α<+ 90°），以及c）在绝缘基板中形成通孔 与步骤a）相同的条件，除了以角度＆bgr辐射激光; 相对于垂直于绝缘基板的表面的线。 角度＆bgr 被设定为相对于垂直于绝缘基板的表面的线的角度α线对称，并且满足＆bgr =α的关系。

公开(公告)号：US08832931B2

公开(公告)日：2014-09-16

申请号：US13159276

申请日：2011-06-13

Applicant: Philip H. Thompson ,  Larry D. Pottebaum

Inventor： Philip H. Thompson ,  Larry D. Pottebaum

IPC: H05K3/30 ,  G02B5/08 ,  G02B5/10 ,  H01L23/00 ,  H01L23/552 ,  H01L23/31 ,  H05K3/00 ,  H05K3/34

CPC classification number: H05K9/0088 ,  H01L23/3121 ,  H01L23/552 ,  H01L24/97 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H05K3/0052 ,  H05K3/3405 ,  H05K3/3442 ,  H05K2201/10204 ,  H05K2201/10371 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49144 ,  H01L2224/85 ,  H01L2924/00

Abstract: An electronic module with an integrated electromagnetic shield using surface mount shield wall components has been disclosed. Each surface mount shield wall component provides side shielding of the circuitry within the overmolded electronic module and provides an exposed conductive shield wall section to which a top conductive shield can be applied. By including the shield structure as part of the overmolded electronic module, the need for a separate shield and separate process steps for installing the separate shield can be eliminated. Each surface mount shield wall component comprises a non-conductive portion that provides stability during a reflow soldering process, but at least a sacrificial portion of the non-conductive portion can be removed to reduce the amount of area occupied by the overmoldable shield structure.

Abstract translation: 已经公开了具有使用表面安装屏蔽壁部件的集成电磁屏蔽的电子模块。 每个表面安装屏蔽壁部件提供了包覆成型的电子模块内的电路的侧面屏蔽，并且提供暴露的导电屏蔽壁部分，可以向其施加顶部导电屏蔽。 通过将屏蔽结构作为包覆成型的电子模块的一部分，可以消除对单独的屏蔽和用于安装单独的屏蔽的单独的工艺步骤的需要。 每个表面安装屏蔽壁部件包括在回流焊接过程期间提供稳定性的非导电部分，但是可以去除非导电部分的至少牺牲部分以减少由可包覆模制的屏蔽结构占据的面积的量。

公开(公告)号：US08604820B2

公开(公告)日：2013-12-10

申请号：US12707930

申请日：2010-02-18

Applicant: Anthony J. Suto

Inventor： Anthony J. Suto

IPC: G01R31/28

CPC classification number: G01R31/2818 ,  H05K1/0268 ,  H05K3/3442 ,  H05K2201/10022 ,  H05K2201/10204 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A reliable and durable method of testing of printed circuit boards is presented. Test access components are placed in contact regions for providing electrical connectivity between test probes and the printed circuit board. In some cases, a test access component may be a surface mount resistor. The test access component may provide two points of contact for test probes to make electrical and mechanical contact with the printed circuit board. Test access components may also provide for increased durability of testing, allowing for a greater number of test contacts to be made between test probes and printed circuit boards than were previously possible.

Abstract translation: 介绍了一种可靠耐用的印刷电路板测试方法。 测试访问组件放置在接触区域中，以提供测试探针与印刷电路板之间的电连接。 在某些情况下，测试访问组件可能是表面贴装电阻。 测试访问组件可以为测试探针提供两个接触点，以与印刷电路板进行电气和机械接触。 测试访问组件还可以提供更高的测试耐久性，允许在测试探针和印刷电路板之间进行比以前更多的测试接触。

公开(公告)号：US08601680B2

公开(公告)日：2013-12-10

申请号：US12545371

申请日：2009-08-21

Applicant: Woo-suk Choi ,  Deok-heung Kim

Inventor： Woo-suk Choi ,  Deok-heung Kim

IPC: H05K3/00 ,  H05K3/20

CPC classification number: H05K3/0085 ,  B65H18/103 ,  B65H23/188 ,  B65H2301/522 ,  B65H2701/1752 ,  H05K1/0393 ,  H05K3/0097 ,  H05K2201/10204 ,  H05K2203/1545

Abstract: Provided is a method of roll-to-roll processing of semiconductor parts, the method including: supplying to a processing unit a first material uncoiled from a first roll for processing at the processing unit; connecting a leading board to a leading portion of the first material before the processing so that the first material led by the leading board is processed during transfer in the processing unit along a path; cutting the leading board from the leading portion of the first material after the processing; and if a terminal edge of the first material begins to be processed at the processing unit, connecting another leading board to a leading portion of a second material uncoiled from a second roll and supplying the second material to the processing unit for processing.

Abstract translation: 提供一种半导体部件的卷对卷处理的方法，该方法包括：向处理单元提供从第一辊展开的第一材料，以在处理单元处进行处理; 在处理之前将前导板连接到第一材料的引导部分，使得由前导板引导的第一材料沿着路径在处理单元中传送期间被处理; 在处理后从第一材料的引导部分切割引导板; 并且如果所述第一材料的端边缘在所述处理单元处开始被处理，则将另一前导板连接到从第二辊展开的第二材料的引导部分，并将所述第二材料供应到所述处理单元用于处理。

公开(公告)号：US08508236B2

公开(公告)日：2013-08-13

申请号：US12959049

申请日：2010-12-02

Applicant: Swen Weitemeier ,  Christian Oldendorf

Inventor： Swen Weitemeier ,  Christian Oldendorf

IPC: H01H31/02

CPC classification number: G01R31/2815 ,  G01R31/2839 ,  G06F21/86 ,  H05K1/0275 ,  H05K2201/10151 ,  H05K2201/10204

Abstract: An electronic device, and associated method, provided with a circuit board (10), with a set of input contacts (IN/COM), a set of output contacts (OUT/COM) and an electrical circuit (18) connected between the input contacts (IN/COM) and the output contacts (OUT/COM) and a controller. The controller carries out a real-time test of the circuit board using a test signal introduced into the electrical circuit, the electrical circuit (18) being designed as a passive network having a characteristic transfer function and provided with at least two separate partial circuits (18′, 18″) wherein the separate partial circuits are electrically connected in the assembled state by cooperation with at least one of: at least one device components and/or assembly components (181).

Abstract translation: 一种具有电路板（10）的电子设备和相关方法，具有一组输入触点（IN / COM），一组输出触点（OUT / COM）和连接在输入端之间的电路（18） 触点（IN / COM）和输出触点（OUT / COM）和控制器。 控制器使用引入电路的测试信号对电路板进行实时测试，电路（18）被设计为具有特征传递功能的无源网络，并且具有至少两个分开的部分电路（ 18'，18“），其中所述分开的部分电路通过与至少一个器件部件和/或组件部件（181）中的至少一个协作而在组装状态下电连接。