中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.015 seconds)

    WRITE BUFFERING
    1.
    发明申请
    WRITE BUFFERING 审中-公开

    公开(公告)号：US20200151098A1

    公开(公告)日：2020-05-14

    申请号：US16601327

    申请日：2019-10-14

    Applicant: BITMICRO LLC

    Inventor： Rolando H. Bruce ,  Elmer Paule Dela Cruz ,  Mark Ian Alcid Arcedera

    IPC: G06F12/0831 ,  G06F12/0875

    Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower. Methods provided here may be extended for systems that have more than two cache levels.

    Multi-dimensional computer storage system
    2.
    发明授权
    Multi-dimensional computer storage system 有权

    公开(公告)号：US10552050B1

    公开(公告)日：2020-02-04

    申请号：US15482684

    申请日：2017-04-07

    Applicant: BiTMICRO LLC

    Inventor： Marlon B. Verdan ,  Ricardo H. Bruce

    IPC: G06F3/06 ,  G06F12/1081

    Abstract: In an embodiment of the invention, an apparatus comprises: a multi-dimensional memory that is expandable in a first direction; wherein the multi-dimensional memory comprises a serial chain; wherein the serial chain comprises a first serial chain that is expandable in a first direction; and wherein the first serial chain comprises a first memory controller, a first memory module coupled to the first memory controller, a second memory controller coupled to the first memory controller, and a second memory module coupled to the second memory controller. In another embodiment of the invention, a method comprises: providing a multi-dimensional memory that is expandable in a first direction; wherein the multi-dimensional memory comprises a serial chain; wherein the serial chain comprises a first serial chain that is expandable in a first direction; and wherein the first serial chain comprises a first memory controller, a first memory module coupled to the first memory controller, a second memory controller coupled to the first memory controller, and a second memory module coupled to the second memory controller. Data can be stored into the serial chain, wherein the data is written by a memory transaction from a host.

    Memory transaction with reduced latency
    3.
    发明授权
    Memory transaction with reduced latency 有权

    公开(公告)号：US10120586B1

    公开(公告)日：2018-11-06

    申请号：US14616700

    申请日：2015-02-07

    Applicant: BITMICRO LLC

    Inventor： Rey H. Bruce ,  Ricardo H. Bruce ,  Elsbeth Lauren Tagayo-Villapana

    IPC: G06F12/00 ,  G06F3/06 ,  G06F13/28

    Abstract: A solution for performing reduced latency memory read transactions is disclosed. In one example, a storage apparatus has a memory array that includes: a flash device having a data register, a memory interface coupled to the memory array and a buffer set that includes at least one buffer suitable for use as a prefetch buffer. The memory interface, in response to a memory read transaction request, performs a read operation and, if stored data exists within the memory array that meets a prefetch selection criterion, also performs an internal read operation. The internal read operation includes allocating a prefetch buffer in the buffer set and storing the data as prefetch data in the prefetch buffer. If the memory interface receives a second memory read transaction request for data that is currently available as prefetch data, the memory interface responds by performing a forwarding transaction that includes retrieving the prefetch data from the prefetch buffer and forwarding the prefetch data to a host.

    MULTILEVEL MEMORY BUS SYSTEM
    7.
    发明申请
    MULTILEVEL MEMORY BUS SYSTEM 审中-公开

    公开(公告)号：US20190087363A1

    公开(公告)日：2019-03-21

    申请号：US16197001

    申请日：2018-11-20

    Applicant: BITMICRO LLC

    Inventor： Ricardo H. Bruce ,  Elsbeth Lauren Tagayo Villapana ,  Joel Alonzo Baylon

    IPC: G06F13/16 ,  G06F12/00 ,  G06F13/36 ,  G06F12/02

    Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.

    Multilevel memory bus system
    9.
    发明授权
    Multilevel memory bus system 有权

    公开(公告)号：US10133686B2

    公开(公告)日：2018-11-20

    申请号：US14297628

    申请日：2014-06-06

    Applicant: BiTMICRO LLC

    Inventor： Ricardo H. Bruce ,  Elsbeth Lauren Tagayo Villapana ,  Joel Alonzo Baylon

    IPC: G06F13/36 ,  G06F13/16 ,  G06F12/00 ,  G06F12/02

    Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.

Patent Agency Ranking