公开(公告)号：US09355910B2

公开(公告)日：2016-05-31

申请号：US13324740

申请日：2011-12-13

Applicant: Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

Inventor： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L21/70 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  H01L27/118

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0847 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

Abstract translation: 提供半导体器件用于实现至少一个逻辑元件。 该半导体器件包括具有第一晶体管的半导体衬底和形成在半导体衬底上的第二晶体管。 每个晶体管包括源极，漏极和栅极。 沟槽硅化物层将第一晶体管的源极或漏极之一电连接到第二晶体管的源极或漏极之一。

公开(公告)号：US08618607B1

公开(公告)日：2013-12-31

申请号：US13539830

申请日：2012-07-02

Applicant: Mahbub Rashed ,  David Doman ,  Marc Tarabbia ,  Irene Lin ,  Jeff Kim ,  Chinh Nguyen ,  Steve Soss ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

Inventor： Mahbub Rashed ,  David Doman ,  Marc Tarabbia ,  Irene Lin ,  Jeff Kim ,  Chinh Nguyen ,  Steve Soss ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L21/02

CPC classification number: H01L27/0207 ,  H01L27/11807

Abstract: One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.

Abstract translation: 本文公开的一个说明性器件包括限定在半导体衬底中的连续有源区，形成在连续有源区中和上方的第一和第二晶体管，第一和第二晶体管中的每一个包括形成在连续有源区中的多个掺杂区， 导电隔离电极位于第一和第二晶体管之间的连续有源区上方，导电隔离电极与导电隔离电极导电耦合。

公开(公告)号：US08598633B2

公开(公告)日：2013-12-03

申请号：US13351101

申请日：2012-01-16

Applicant: Marc Tarabbia ,  James B. Gullette ,  Mahbub Rashed ,  David S. Doman ,  Irene Y. Lin ,  Ingolf Lorenz ,  Larry Ho ,  Chinh Nguyen ,  Jeff Kim ,  Jongwook Kye ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Jason E. Stephens ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

Inventor： Marc Tarabbia ,  James B. Gullette ,  Mahbub Rashed ,  David S. Doman ,  Irene Y. Lin ,  Ingolf Lorenz ,  Larry Ho ,  Chinh Nguyen ,  Jeff Kim ,  Jongwook Kye ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Jason E. Stephens ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/52

CPC classification number: H01L23/5286 ,  H01L21/76895 ,  H01L21/823475 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.

Abstract translation: 半导体器件包括具有扩散区域的半导体衬底。 晶体管形成在扩散区内。 电力轨设置在扩散区域的外侧。 接触层设置在基板上方和电源轨下方。 通孔设置在接触层和电源轨之间以将接触层电连接到电源轨。 接触层包括设置在扩散区域外部的第一长度和从第一长度延伸到扩散区域并电连接到晶体管的第二长度。

公开(公告)号：US07167373B1

公开(公告)日：2007-01-23

申请号：US10796540

申请日：2004-03-08

Applicant: Phan Hoang ,  Chinh Nguyen ,  Frank Hoang ,  Andy Le

Inventor： Phan Hoang ,  Chinh Nguyen ,  Frank Hoang ,  Andy Le

IPC: H05K7/06

CPC classification number: H05K1/189 ,  H01L23/3128 ,  H01L23/5387 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/1627 ,  H05K3/0058 ,  H05K2201/042 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/2009 ,  Y10T29/49144

Abstract: One embodiment of the invention includes a flexible circuit and a stiffener. The flexible circuit has first, second, and third portions. The first portion is folded on an upper surface of the third portion and has first contact elements attached to a first device. The second portion is folded on the first device and has second contact elements attached to a second device. The stiffener is attached to the upper surface of the third portion and located between the upper surface of the third portion and the first portion.

Abstract translation: 本发明的一个实施例包括柔性电路和加强件。 柔性电路具有第一，第二和第三部分。 第一部分折叠在第三部分的上表面上，并且具有附接到第一装置的第一接触元件。 第二部分折叠在第一装置上，并且具有附接到第二装置的第二接触元件。 加强件附接到第三部分的上表面并且位于第三部分的上表面和第一部分之间。

公开(公告)号：US20190326219A1

公开(公告)日：2019-10-24

申请号：US16502521

申请日：2019-07-03

Applicant: Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

Inventor： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/535 ,  H01L29/08 ,  H01L27/092 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/285 ,  H01L27/02 ,  H01L21/768

Abstract: A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.

公开(公告)号：US20140027918A1

公开(公告)日：2014-01-30

申请号：US13561932

申请日：2012-07-30

Applicant: Mahbub Rashed ,  Marc Tarabbia ,  Chinh Nguyen ,  David Doman ,  Juhan Kim ,  Xiang Qi ,  Suresh Venkatesan

Inventor： Mahbub Rashed ,  Marc Tarabbia ,  Chinh Nguyen ,  David Doman ,  Juhan Kim ,  Xiang Qi ,  Suresh Venkatesan

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5381 ,  G06F17/5068 ,  G06F2217/12 ,  H01L21/768 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11861 ,  H01L2027/11874 ,  H01L2924/0002 ,  Y02P90/265 ,  Y02T10/82 ,  H01L2924/00

Abstract: An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.

Abstract translation: 公开了一种使用扩散接触结构提供基于交叉耦合的设计的方法。 实施例包括在衬底上提供第一和第二栅极结构; 提供跨越第一栅极结构的第一栅极截止区域和穿过第二栅极结构的第二栅极截止区域; 在所述第一栅极结构上提供第一栅极接触，以及在所述第二栅极结构上方的第二栅极接触; 以及在所述第一和第二栅极切割区域之间提供扩散接触结构，以将所述第一栅极接触耦合到所述第二栅极接触。

公开(公告)号：US20130181289A1

公开(公告)日：2013-07-18

申请号：US13351101

申请日：2012-01-16

Applicant: Marc Tarabbia ,  James B. Gullette ,  Mahbub Rashed ,  David S. Doman ,  Irene Y. Lin ,  Ingolf Lorenz ,  Larry Ho ,  Chinh Nguyen ,  Jeff Kim ,  Jongwook Kye ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Jason E. Stephens ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

Inventor： Marc Tarabbia ,  James B. Gullette ,  Mahbub Rashed ,  David S. Doman ,  Irene Y. Lin ,  Ingolf Lorenz ,  Larry Ho ,  Chinh Nguyen ,  Jeff Kim ,  Jongwook Kye ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Jason E. Stephens ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L23/5286 ,  H01L21/76895 ,  H01L21/823475 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.

Abstract translation: 半导体器件包括具有扩散区域的半导体衬底。 晶体管形成在扩散区内。 电力轨设置在扩散区域的外侧。 接触层设置在基板上方和电源轨下方。 通孔设置在接触层和电源轨之间以将接触层电连接到电源轨。 接触层包括设置在扩散区域外部的第一长度和从第一长度延伸到扩散区域并电连接到晶体管的第二长度。

公开(公告)号：US08124450B2

公开(公告)日：2012-02-28

申请号：US12844795

申请日：2010-07-27

Applicant: Phan Hoang ,  Chinh Nguyen ,  Anthony Tran ,  Tung Dang

Inventor： Phan Hoang ,  Chinh Nguyen ,  Anthony Tran ,  Tung Dang

IPC: H01L21/00

CPC classification number: H01L23/3107 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/06572 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/15159 ,  H05K1/141 ,  H05K1/144 ,  H05K1/182 ,  H05K3/3436 ,  H05K2201/049 ,  H05K2201/09036 ,  H05K2201/10515 ,  H05K2201/10674

Abstract: An embodiment of the present invention is a technique to stack multiple devices using an interconnecting element. A board has a periphery and top and bottom surfaces. The top surface has top contact pads to attach to a first device. The bottom surface is milled down to form a cavity confined by vertical walls around the periphery. The cavity fits a second device. Bottom contact pads are formed on bottom side of the vertical walls. The bottom contact pads are raised with respect to the bottom side of the vertical walls. Traces internal to the board connect the bottom contact pads to the top contact pads.

Abstract translation: 本发明的实施例是使用互连元件堆叠多个设备的技术。 电路板具有外围和顶部和底部表面。 顶表面具有附接到第一装置的顶部接触垫。 底面被铣削以形成围绕周边的垂直壁限定的空腔。 该腔适合第二个装置。 底部接触垫形成在垂直壁的底侧。 底部接触垫相对于垂直壁的底侧升高。 电路板内部的跟踪将底部接触焊盘连接到顶部接触焊盘。

公开(公告)号：US10731305B2

公开(公告)日：2020-08-04

申请号：US16159714

申请日：2018-10-15

Applicant: Dinh Chinh Nguyen

Inventor： Dinh Chinh Nguyen

IPC: E01D15/22 ,  B60F3/00 ,  F02B61/04

Abstract: A fast installing self-propelled pontoon bridge consisting of the entrance vehicle (A-1), a vehicle-float which is connected with the entrance vehicle and an exit vehicle, an exit vehicle, and an anchoring vehicle to keep the bridge in one place, being equipped with an anchor to keep the pontoon bridge to resist the water flow.

公开(公告)号：US08581348B2

公开(公告)日：2013-11-12

申请号：US13324699

申请日：2011-12-13

Applicant: Mahbub Rashed ,  Steven Soss ,  Jongwook Kye ,  Irene Y. Lin ,  James Benjamin Gullette ,  Chinh Nguyen ,  Jeff Kim ,  Marc Tarabbia ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

Inventor： Mahbub Rashed ,  Steven Soss ,  Jongwook Kye ,  Irene Y. Lin ,  James Benjamin Gullette ,  Chinh Nguyen ,  Jeff Kim ,  Marc Tarabbia ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L27/088 ,  H01L21/70 ,  H01L21/02

CPC classification number: H01L21/76895 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.

Abstract translation: 提供半导体器件用于实现至少一个逻辑元件。 半导体器件包括具有第一晶体管的半导体衬底和形成在半导体衬底上的第二晶体管。 每个晶体管包括源极，漏极和栅极。 CA层电连接到第一晶体管的源极或漏极中的至少一个。 CB层电连接到晶体管和CA层的至少一个栅极。