公开(公告)号：US11862604B2

公开(公告)日：2024-01-02

申请号：US17240364

申请日：2021-04-26

Applicant: ADEIA SEMICONDUCTOR INC.

Inventor： Javier A. Delacruz ,  Belgacem Haba ,  Cyprian Emeka Uzoh ,  Rajesh Katkar ,  Ilyas Mohammed

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L24/11 ,  H01L2224/08146 ,  H01L2224/119 ,  H01L2224/11464 ,  H01L2224/13005 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06555

Abstract: An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.

公开(公告)号：US20240162190A1

公开(公告)日：2024-05-16

申请号：US18523665

申请日：2023-11-29

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. DeLaCruz ,  Belgacem Haba ,  Cyprian Emeka Uzoh ,  Rajesh Katkar ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L24/11 ,  H01L2224/08146 ,  H01L2224/11464 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06555

Abstract: An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.