公开(公告)号：US20250105122A1

公开(公告)日：2025-03-27

申请号：US18976255

申请日：2024-12-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

公开(公告)号：US20240088091A1

公开(公告)日：2024-03-14

申请号：US17940827

申请日：2022-09-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin SHIH ,  Chih-Cheng LEE

IPC: H01L23/00

CPC classification number: H01L24/97 ,  H01L2224/95136

Abstract: A method for manufacturing a package structure includes: providing a first electrical element and a second electrical element on a surface of a first carrier, wherein the second electrical element is shifted with respect to the first electrical element; and moving the first electrical element along at least one direction substantially parallel with the surface of the first carrier until a first surface of the first electrical element is substantially aligned with a first surface of the second electrical element from a top view.

公开(公告)号：US20210035908A1

公开(公告)日：2021-02-04

申请号：US16528352

申请日：2019-07-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Cheng LEE ,  Kuang Hsiung CHEN

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

Abstract: A semiconductor device package includes a first circuit layer, a second circuit layer, a first semiconductor die and a second semiconductor die. The first circuit layer includes a first surface and a second surface opposite to the first surface. The second circuit layer is disposed on the first surface of the first circuit layer. The first semiconductor die is disposed on the first circuit layer and the second circuit layer, and electrically connected to the first circuit layer and the second circuit layer. The second semiconductor die is disposed on the second circuit layer, and electrically connected to the second circuit layer.

公开(公告)号：US20190287867A1

公开(公告)日：2019-09-19

申请号：US16297451

申请日：2019-03-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

IPC: H01L21/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A substrate structure includes a wiring structure and a supporter. The wiring structure includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is disposed on the first dielectric structure. The second dielectric structure covers the first dielectric structure and the first circuit layer. A pad portion of the first circuit layer is exposed from the first dielectric structure, and the second circuit layer protrudes from the second dielectric structure. The supporter is disposed adjacent to the first dielectric structure of the wiring structure, and defines at least one through hole corresponding to the exposed pad portion of the first circuit layer.

公开(公告)号：US20180166370A1

公开(公告)日：2018-06-14

申请号：US15379362

申请日：2016-12-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chai-Chi LIN ,  Chih-Cheng LEE ,  Hsing Kuo TIEN ,  Chih-Yung YANG

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L25/16 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/16225

Abstract: A semiconductor substrate includes an interconnection structure and a dielectric layer. The dielectric layer surrounds the interconnection structure and defines a first cavity. The first cavity is defined by a first sidewall, a second sidewall, and a first surface of the dielectric layer. The first sidewall is laterally displaced from the second sidewall.

公开(公告)号：US20170231093A1

公开(公告)日：2017-08-10

申请号：US15019776

申请日：2016-02-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin HO ,  Chih-Cheng LEE ,  Po-Shu PENG

IPC: H05K1/11 ,  H05K3/10 ,  H05K3/40

CPC classification number: H05K1/116 ,  H05K3/0035 ,  H05K3/10 ,  H05K3/4038

Abstract: A package substrate includes a dielectric layer, a conductive via disposed in the dielectric layer, and a conductive pattern layer exposed from a first surface of the dielectric layer. The conductive pattern layer includes traces and a via land, the via land extends into the conductive via, and a circumferential portion of the via land is encompassed by the conductive via. A method of making a package substrate includes forming a conductive pattern layer including traces and a via land, providing a dielectric layer to cover the conductive pattern layer, and forming a via hole. Forming the via hole is performed by removing a portion of the dielectric layer and exposing a bottom surface of the via land and at least a portion of a side surface of the via land. A conductive material is applied into the via hole to form a conductive via covering the via land.

公开(公告)号：US20160150651A1

公开(公告)日：2016-05-26

申请号：US14550615

申请日：2014-11-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H05K1/18 ,  H05K3/00 ,  H05K3/34 ,  H01L21/48 ,  H01L23/498

CPC classification number: H05K1/186 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K3/007 ,  H05K3/34 ,  H05K2203/06 ,  H01L2924/00

Abstract: The present disclosure relates to a semiconductor device substrate and a method for making the same. The semiconductor device substrate includes a first dielectric layer, a second dielectric layer and an electronic component. The first dielectric layer includes a body portion, and a wall portion protruded from a first surface of the body portion. The wall portion has an end. The second dielectric layer has a first surface and an opposing second surface. The first surface of the second dielectric layer is adjacent to the first surface of the body portion. The second dielectric layer surrounds the wall portion. The end of the wall portion extends beyond the second surface of the second dielectric layer. The electronic component includes a first electrical contact and a second electrical contact. At least a part of the electronic component is surrounded by the wall portion.

Abstract translation: 本公开涉及一种半导体器件基板及其制造方法。 半导体器件基板包括第一介电层，第二介电层和电子部件。 第一电介质层包括主体部分和从主体部分的第一表面突出的壁部分。 壁部分有一端。 第二电介质层具有第一表面和相对的第二表面。 第二电介质层的第一表面与主体部分的第一表面相邻。 第二电介质层围绕壁部。 壁部分的端部延伸超过第二介电层的第二表面。 电子部件包括第一电接触和第二电接触。 电子部件的至少一部分被壁部包围。

公开(公告)号：US20130068517A1

公开(公告)日：2013-03-21

申请号：US13673868

申请日：2012-11-09

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING,

Inventor： Chih-Cheng LEE

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K3/0023 ,  H05K3/04 ,  H05K3/045 ,  H05K3/06 ,  H05K3/10 ,  H05K3/108 ,  H05K3/4038 ,  H05K3/4644 ,  H05K3/465 ,  H05K2201/0352 ,  H05K2203/025 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method for manufacturing a substrate structure is provided. The method includes the following steps. A substrate is provided. The substrate has a patterned first metal layer, a pattern second metal layer and a through hole. After that, a first dielectric layer and a second dielectric layer are formed at a first surface and a second surface of the substrate, respectively. The second surface is opposite to the first surface. Then, the first dielectric layer and the second dielectric layer are patterned. After that, a first trace layer is formed at a surface of the patterned first dielectric layer. The first trace layer is embedded into the patterned first dielectric layer and is coplanar with the first dielectric layer. Then, a second trace layer is formed on a surface of the second dielectric layer.

Abstract translation: 提供了一种用于制造衬底结构的方法。 该方法包括以下步骤。 提供基板。 衬底具有图案化的第一金属层，图案第二金属层和通孔。 之后，分别在基板的第一表面和第二表面上形成第一电介质层和第二电介质层。 第二表面与第一表面相对。 然后，对第一电介质层和第二电介质层进行图案化。 之后，在图案化的第一介电层的表面形成第一迹线层。 第一迹线层被嵌入到图案化的第一介电层中并且与第一介电层共面。 然后，在第二电介质层的表面上形成第二迹线层。

公开(公告)号：US20230387092A1

公开(公告)日：2023-11-30

申请号：US18231767

申请日：2023-08-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Mei HUANG ,  Shih-Yu WANG ,  I-Ting LIN ,  Wen Hung HUANG ,  Yuh-Shan SU ,  Chih-Cheng LEE ,  Hsing Kuo TIEN

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/528

CPC classification number: H01L25/16 ,  H01L23/3171 ,  H01L23/315 ,  H01L23/3128 ,  H01L24/17 ,  H01L23/5226 ,  H01L21/563 ,  H01L23/5283 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L23/293

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

公开(公告)号：US20210398904A1

公开(公告)日：2021-12-23

申请号：US16907059

申请日：2020-06-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

IPC: H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H01Q1/22 ,  H01L21/768

Abstract: A semiconductor device package includes a substrate, and interconnection structure and a package body. The interconnection structure is disposed on the substrate. The interconnection structure has a conductive structure and a first dielectric layer covering a portion of the conductive structure. The conductive structure defines an antenna feeding point. The package body is disposed on the substrate and covers the interconnection structure.