公开(公告)号：US20210317580A1

公开(公告)日：2021-10-14

申请号：US16848784

申请日：2020-04-14

Applicant: APPLIED MATERIALS, INC.

Inventor： Shi YOU ,  He REN ,  Naomi YOSHIDA ,  Nikolaos BEKIARIS ,  Mehul NAIK ,  Martin Jay SEAMONS ,  Jingmei LIANG ,  Mei-Yee SHEK

IPC: C23C16/56 ,  H01L21/768

Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material

公开(公告)号：US20240379420A1

公开(公告)日：2024-11-14

申请号：US18781633

申请日：2024-07-23

Applicant: APPLIED MATERIALS, INC.

Inventor： Shi YOU ,  He REN ,  Naomi YOSHIDA ,  Nikolaos BEKIARIS ,  Mehul NAIK ,  Martin Jay SEAMONS ,  Jingmei LIANG ,  Mei-Yee SHEK

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/67

Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material

公开(公告)号：US20240363354A1

公开(公告)日：2024-10-31

申请号：US18636449

申请日：2024-04-16

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Raman GAIRE ,  Shi YOU ,  Pranav RAMESH ,  Houssam LAZKANI ,  Shawn THOMAS ,  Abhishek DUBE ,  Mehul B. NAIK ,  Songkram Sonny SRIVATHANAKUL

IPC: H01L21/285 ,  C30B25/18 ,  C30B29/06 ,  C30B29/68 ,  H01L21/768 ,  H01L29/40

CPC classification number: H01L21/28518 ,  C30B25/18 ,  C30B29/06 ,  C30B29/68 ,  H01L21/768 ,  H01L29/401

Abstract: Semiconductor devices and methods for manufacturing the same are provided. The method includes epitaxially growing a doped crystalline silicon-containing layer over a source/drain feature and growing a doped amorphous silicon-containing layer over a field region of a semiconductor layer. The trench is formed in the semiconductor layer and the trench exposes the source/drain feature. The method further includes epitaxially growing an undoped crystalline silicon-containing capping layer over the doped crystalline silicon-containing layer and growing an undoped amorphous silicon-containing layer over the doped silicon-containing amorphous layer. The method further includes selectively removing the doped amorphous silicon-containing layer and the undoped amorphous silicon-containing layer relative to the silicon-containing crystalline capping layer. The method further includes removing the silicon-containing crystalline capping layer to expose the doped silicon-containing crystalline layer.

公开(公告)号：US20230187276A1

公开(公告)日：2023-06-15

申请号：US18108338

申请日：2023-02-10

Applicant: APPLIED MATERIALS, INC.

Inventor： Shi YOU ,  He REN ,  Naomi YOSHIDA ,  Nikolaos BEKIARIS ,  Mehul NAIK ,  Jay Martin SEAMONS ,  Jingmei LIANG ,  Mei-Yee SHEK

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01L21/76837 ,  H01L21/76828 ,  H01L21/76826 ,  H01L21/02337 ,  H01L21/76825 ,  H01L21/02323 ,  H01L21/76834 ,  H01L21/67103 ,  H01L21/02326

Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material

公开(公告)号：US20220181201A1

公开(公告)日：2022-06-09

申请号：US17110826

申请日：2020-12-03

Applicant: Applied Materials, Inc.

Inventor： Yi XU ,  Yufei HU ,  He REN ,  Yu LEI ,  Shi YOU ,  Kazuya DAITO

IPC: H01L21/768

Abstract: Embodiments of the disclosure provide methods which reduce or eliminate lateral growth of a selective tungsten layer. Further embodiments provide an integrated clean and deposition method which improves the selectivity of selectively deposited tungsten on trench structures. Additional embodiments provide methods for forming a more uniform and selective bottom-up gap fill for trench structures with improved film properties.

公开(公告)号：US20210074583A1

公开(公告)日：2021-03-11

申请号：US16562091

申请日：2019-09-05

Applicant: Applied Materials, Inc.

Inventor： Shi YOU ,  He REN ,  Mehul B. NAIK

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Embodiments of the present disclosure generally relate an interconnect structure formed on a substrate and a method of forming the interconnect structure thereon. In one embodiment, a method of forming an interconnect structure includes forming an opening comprising a via and a trench in an insulating structure formed on a substrate, forming a first passivation layer in the opening, removing a portion of the first passivation layer from the opening, and selectively depositing a first metal containing material in the via.

公开(公告)号：US20210066064A1

公开(公告)日：2021-03-04

申请号：US17004850

申请日：2020-08-27

Applicant: APPLIED MATERIALS, INC.

Inventor： He REN ,  Shi YOU ,  Hao JIANG ,  Raymond HUNG ,  Mehul NAIK ,  Chentsau Chris YING ,  Mang-Mang LING ,  Lin DONG

IPC: H01L21/02

Abstract: Methods and apparatus for cleaning a contaminated metal surface on a substrate, including: exposing a substrate including a dielectric surface and a metal surface including metal nitride residues and metal carbide residues to a process gas including an oxidizing agent to form a substrate including a dielectric surface and a metal surface including metal oxides residues; and exposing a substrate including a dielectric surface and a metal surface including metal oxides residues to a process gas including a reducing agent to form a substrate including a dielectric surface and a substantially pure metal surface.

公开(公告)号：US20240213088A1

公开(公告)日：2024-06-27

申请号：US18595951

申请日：2024-03-05

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Hao JIANG ,  Shi YOU ,  Mehul B. NAIK

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76879

Abstract: Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 μΩ·cm or less.

公开(公告)号：US20240038541A1

公开(公告)日：2024-02-01

申请号：US17961153

申请日：2022-10-06

Applicant: Applied Materials, Inc.

Inventor： Jiajie CEN ,  Xiaodong WANG ,  Kevin KASHEFI ,  Shi YOU

IPC: H01L21/3065

CPC classification number: H01L21/3065

Abstract: Methods for cleaning oxides from a substrate surface are performed without affecting low-k dielectric or carbon materials on the substrate. In some embodiments, the method may include performing a preclean process with a chlorine-based soak to remove oxides from a surface of a substrate in a back end of the line (BEOL) process and treating the surface of the substrate with a remote plasma with a hydrogen gas and at least one inert gas to remove residual chlorine residue from the surface of the substrate without damaging low-k dielectric material or carbon material on the substrate.

公开(公告)号：US20220285212A1

公开(公告)日：2022-09-08

申请号：US17193994

申请日：2021-03-05

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Hao JIANG ,  Shi YOU ,  Mehul B. NAIK

IPC: H01L21/768

Abstract: Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 μΩ·cm or less.