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    HYBRID BINNING
    1.
    发明申请
    HYBRID BINNING 有权

    公开(公告)号：US20210225060A1

    公开(公告)日：2021-07-22

    申请号：US17033259

    申请日：2020-09-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Mika Tuomi ,  Kiia Kallio ,  Ruijin Wu ,  Anirudh R. Acharya ,  Vineet Goel

    IPC: G06T15/00 ,  G06T15/08 ,  G06T1/20

    Abstract: A processing device and a method of tiled rendering of an image for display is provided. The processing device includes memory and a processor. The processor is configured to receive the image comprising one or more three dimensional (3D) objects, divide the image into tiles, execute coarse level tiling for the tiles of the image and execute fine level tiling for the tiles of the image. The processing device also includes same fixed function hardware used to execute the coarse level tiling and the fine level tiling. The processor is also configured to determine visibility information for a first one of the tiles. The visibility information is divided into draw call visibility information and triangle visibility information for each remaining tile of the image.

    SYNCHRONIZATION FREE CROSS PASS BINNING THROUGH SUBPASS INTERLEAVING
    4.
    发明申请
    SYNCHRONIZATION FREE CROSS PASS BINNING THROUGH SUBPASS INTERLEAVING 有权

    公开(公告)号：US20220309729A1

    公开(公告)日：2022-09-29

    申请号：US17565394

    申请日：2021-12-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ruijin Wu ,  Mika Tuomi ,  Paavo Sampo Ilmari Pessi ,  Anirudh R. Acharya

    IPC: G06T15/00 ,  G06T1/20

    Abstract: A method of tiled rendering is provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles and interleaving execution of same subpasses of multiple tiles of the frame. Interleaving execution of same subpasses of multiple tiles comprises executing a previously ordered first subpass of a second tile between execution of the previously ordered first subpass of a first tile and execution of a subsequently ordered second subpass of the first tile. The interleaving is performed, for example, by executing the plurality of subpasses in an order different from the order in which the commands to execute the plurality of subpasses are stored and issued. Alternatively, interleaving is performed by executing one or more subpasses as skip operations such that the plurality of subpasses are executed in the same order.

    Single pass flexible screen/scale rasterization
    5.
    发明授权
    Single pass flexible screen/scale rasterization 有权

    公开(公告)号：US10546365B2

    公开(公告)日：2020-01-28

    申请号：US15843968

    申请日：2017-12-15

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： Michael Mantor ,  Laurent Lefebvre ,  Mika Tuomi ,  Kiia Kallio

    IPC: G06T3/40 ,  G06T1/20 ,  G06T3/00 ,  G06T15/80 ,  G06T15/00

    Abstract: An apparatus, such as a head mounted device (HMD), includes one or more processors configured to implement a graphics pipeline that renders pixels in window space with a nonuniform pixel spacing. The apparatus also includes a first distortion function that maps the non-uniformly spaced pixels in window space to uniformly spaced pixels in raster space. The apparatus further includes a scan converter configured to sample the pixels in window space through the first distortion function. The scan converter is configured to render display pixels used to generate an image for display to a user based on the uniformly spaced pixels in raster space. In some cases, the pixels in the window space are rendered such that a pixel density per subtended area is constant across the user's field of view.

    Light volume rendering
    8.
    发明授权
    Light volume rendering 有权

    公开(公告)号：US11551398B2

    公开(公告)日：2023-01-10

    申请号：US17008388

    申请日：2020-08-31

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Mika Tuomi ,  Miikka Petteri Kangasluoma ,  Jan Henrik Achrenius ,  Laurent Lefebvre

    IPC: G06T15/00 ,  G06T15/40 ,  G06T15/80 ,  G06T17/10 ,  G06T7/00 ,  G06T1/20

    Abstract: Systems, apparatuses, and methods for implementing light volume rendering techniques are disclosed. A processor is coupled to a memory. A processor renders the geometry of a scene into a geometry buffer. For a given light source in the scene, the processor initiates two shader pipeline passes to determine which pixels in the geometry buffer to light. On the first pass, the processor renders a front-side of a light volume corresponding to the light source. Any pixels of the geometry buffer which are in front of the front-side of the light volume are marked as pixels to be discarded. Then, during the second pass, only those pixels which were not marked to be discarded are sent to the pixel shader. This approach helps to reduce the overhead involved in applying a lighting effect to the scene by reducing the amount of work performed by the pixel shader.

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