公开(公告)号：US11818877B2

公开(公告)日：2023-11-14

申请号：US17486631

申请日：2021-09-27

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Sung-Kwan Kang ,  Fredrick Fishburn ,  Gill Yong Lee ,  Nitin K. Ingle

IPC: H10B12/00

CPC classification number: H10B12/05 ,  H10B12/03 ,  H10B12/30

Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.

公开(公告)号：US12284803B2

公开(公告)日：2025-04-22

申请号：US17688602

申请日：2022-03-07

Applicant: Applied Materials, Inc.

Inventor： Nicolas Louis Breil ,  Fredrick Fishburn ,  Byeong Chan Lee

IPC: H01L27/108 ,  H10B12/00

Abstract: The present disclosure generally relates to dynamic random access memory (DRAM) devices and to semiconductor fabrication for DRAM devices. Certain embodiments disclosed herein provide an integrated processing system and methods for forming CMOS contact, DRAM array bit line contact (BLC), and storage node structures. The integrated processing system and methods enable deposition of contact and storage node layers with reduced contamination and improved quality, thus reducing leakage current and resistance for the final contact and storage node structures.

公开(公告)号：US11974423B2

公开(公告)日：2024-04-30

申请号：US17551903

申请日：2021-12-15

Applicant: Applied Materials, Inc.

Inventor： Fredrick Fishburn ,  Arvind Kumar ,  Sony Varghese

IPC: H10B12/00

CPC classification number: H10B12/05 ,  H10B12/03

Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) devices and replacement channel processes for fabricating 3D DRAM devices. In an example, a gate dielectric layer is formed on a sacrificial material, and a gate electrode is formed on the gate dielectric layer. After the gate electrode is formed, the sacrificial material is removed and replaced by a semiconductor material. A channel region of a device (e.g., a transistor) that includes the gate dielectric layer and gate electrode is formed in the semiconductor material. The channel region can be vertical or horizontal with respect to a main surface of a substrate on which the device is formed. A capacitor can be formed, such as before or after the semiconductor material is formed, and is electrically connected to the semiconductor material. The device and the capacitor together can form at least part of a 3D DRAM cell.

公开(公告)号：US11696433B2

公开(公告)日：2023-07-04

申请号：US17307366

申请日：2021-05-04

Applicant: Applied Materials, Inc.

Inventor： Nitin K. Ingle ,  Fredrick Fishburn

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05

Abstract: Memory devices and methods of manufacturing memory devices are provided. Described are devices and methods where 3D pitch multiplication decouples high aspect ratio etch width from cell width, creating small cell active area pitch to allow for small DRAM die size.

公开(公告)号：US20230178365A1

公开(公告)日：2023-06-08

申请号：US17994592

申请日：2022-11-28

Applicant: Applied Materials, Inc.

Inventor： Wei Liu ,  Fredrick Fishburn ,  Hailing Liu

IPC: H01L21/02

CPC classification number: H01L21/02247 ,  H01L21/02153 ,  H01L21/0217 ,  H01L21/02252

Abstract: Semiconductor devices and methods of forming semiconductor devices are described. A method of forming metal silicon nitride films is disclosed. Some embodiments of the disclosure provide a process using ammonia plasma for treating a metal silicide or metal film to form a metal silicon nitride film. The ammonia plasma treatment generates NH* radicals that diffuse through the metal silicide to form a metal silicon nitride film that is substantially free of silicon nitride (SiN). The metal silicon nitride films have improved resistance relative to films deposited by thermal processes or plasma processes with a nitrogen plasma exposure.

公开(公告)号：US20220319601A1

公开(公告)日：2022-10-06

申请号：US17705744

申请日：2022-03-28

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Qian Fu ,  Sung-Kwan Kang ,  Takehito Koshizawa ,  Fredrick Fishburn

IPC: G11C16/04 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.

公开(公告)号：US20250126774A1

公开(公告)日：2025-04-17

申请号：US18403930

申请日：2024-01-04

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Sony Varghese ,  Tong Liu ,  Fredrick Fishburn

IPC: H10B12/00

Abstract: Memory devices are provided which have stacked DRAM cells, resulting in an increase in DRAM cell bit-density. In a 3D DRAM with stacked unit cell layers of one or more embodiments, it is necessary to reduce the area of a unit cell in order to increase bit density per unit area for a given number of stacked cells. In one or more embodiments, n wordlines (nWL, n is an integer≥2) share a contact pad. The shared nWLs are separated by n bitlines (BLs) to assign every cell independently one WL and one BL.

公开(公告)号：US12148475B2

公开(公告)日：2024-11-19

申请号：US17705744

申请日：2022-03-28

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Qian Fu ,  Sung-Kwan Kang ,  Takehito Koshizawa ,  Fredrick Fishburn

IPC: G11C16/04 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.

公开(公告)号：US20240038833A1

公开(公告)日：2024-02-01

申请号：US18222086

申请日：2023-07-14

Applicant: Applied Materials, Inc.

Inventor： Fredrick Fishburn ,  Tomohiko Kitajima ,  Qian Fu ,  Srinivas Guggilla ,  Hang Yu ,  Jun Feng ,  Shih Chung Chen ,  Lakmal C. Kalutarage ,  Jayden Potter ,  Karthik Janakiraman ,  Deenesh Padhi ,  Yifeng Zhou ,  Yufeng Jiang ,  Sung-Kwan Kang

IPC: H10B12/00

CPC classification number: H01L28/91 ,  H01L28/92 ,  H10B12/03 ,  H10B12/30

Abstract: Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described where carbon is used as the removable mold material for the formation of a DRAM capacitor. A dense, high-temperature (500° C. or greater) PECVD carbon material is used as the removable mold material, e.g., the core material, instead of oxide. The carbon material can be removed by isotropic etching with exposure to radicals of oxygen (O2), nitrogen (N2), hydrogen (H2), ammonia (NH3), and combinations thereof.

公开(公告)号：US20230309295A1

公开(公告)日：2023-09-28

申请号：US18122373

申请日：2023-03-16

Applicant: Applied Materials, Inc.

Inventor： Fredrick Fishburn ,  Sung-Kwan Kang

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/34 ,  H10B12/053

Abstract: Provided is a DRAM device having a support layer to hold the bWL features before being filled with the electrode metal. The support layer keeps the structure supported from the top surface but does not prevent the gap fill. A temporary gap-fill material is first deposited in the bWL gaps and then recessed to expose the top edges. A support layer material is then deposited on the structure by plasma enhanced chemical vapor deposition (PECVD). The device is then patterned orthogonal and with pitch greater than the bWL pitch. The temporary gap-fill material is then removed, forming support beams comprising the support material. A metal can then be deposited to fill the bWL gaps under the support beams.