公开(公告)号：US20240047267A1

公开(公告)日：2024-02-08

申请号：US18228300

申请日：2023-07-31

Applicant: Applied Materials, Inc.

Inventor： Tsung-Han YANG ,  Shiyu YUE ,  Rongjun WANG

IPC: H01L21/768 ,  H01J37/32 ,  C23C14/56 ,  C23C14/58 ,  C23C16/06 ,  C23C14/06 ,  C23C16/455 ,  C23C14/18

CPC classification number: H01L21/76826 ,  H01L21/76843 ,  H01L21/76877 ,  H01J37/32091 ,  H01J37/32899 ,  C23C14/568 ,  C23C14/5846 ,  C23C16/06 ,  C23C14/0641 ,  C23C16/45525 ,  C23C14/18 ,  H01J2237/332

Abstract: Embodiments of methods and associated apparatus for filling features in a silicon-containing dielectric layer of a substrate are provided herein. In some embodiments, a method of filling features in a silicon-containing dielectric layer of a substrate includes: depositing a discontinuous liner layer in the feature via a physical vapor deposition (PVD) process in a first process chamber; performing a hydrogen plasma process in a second process chamber to form silicon-hydrogen bonds on surfaces of the feature not covered by the discontinuous liner layer; and depositing a bulk tungsten layer on the discontinuous liner layer and over the silicon-hydrogen bonds to fill the feature with tungsten in a third process chamber.

公开(公告)号：US20230343644A1

公开(公告)日：2023-10-26

申请号：US18070383

申请日：2022-11-28

Applicant: Applied Materials, Inc.

Inventor： Chih-Hsun HSU ,  Shiyu YUE ,  Jiang LU ,  Rongjun WANG ,  Xianmin TANG ,  Zhenjiang CUI ,  Chi Hong CHING ,  Meng-Shan WU ,  Chun-chieh WANG ,  Wei LEI ,  Yu LEI

IPC: H01L21/768 ,  H01L21/67 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/67063 ,  H01L21/6719 ,  H01L21/76843 ,  H01L21/76871 ,  H01L23/53266

Abstract: A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed in a first process chamber to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process is performed in the first process chamber removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.

公开(公告)号：US20230343643A1

公开(公告)日：2023-10-26

申请号：US17868475

申请日：2022-07-19

Applicant: Applied Materials, Inc.

Inventor： Chih-Hsun HSU ,  Shiyu YUE ,  Wei LEI ,  Yi XU ,  Jiang LU ,  Yu LEI ,  Ziye XIONG ,  Tsung-Han YANG ,  Zhimin QI ,  Aixi ZHANG ,  Jie ZHANG ,  Liqi WU ,  Rongjun WANG ,  Shihchung CHEN ,  Meng-Shan WU ,  Chun-Chieh WANG ,  Annamalai LAKSHMANAN ,  Yixiong YANG ,  Xianmin TANG

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76877 ,  H01L21/76876 ,  H01L21/76843 ,  H01L21/76865 ,  H01L23/5226 ,  H01L21/76826

Abstract: A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.

公开(公告)号：US20230326791A1

公开(公告)日：2023-10-12

申请号：US17718242

申请日：2022-04-11

Applicant: Applied Materials, Inc.

Inventor： Zhimin QI ,  Yi XU ,  Shirish A. PETHE ,  Xingyao GAO ,  Shiyu YUE ,  Aixi ZHANG ,  Wei LEI ,  Yu LEI ,  Geraldine VASQUEZ ,  Dien-yeh WU ,  Da HE

IPC: H01L21/768 ,  H01L21/285 ,  C23C14/18 ,  C23C16/14

CPC classification number: H01L21/76879 ,  H01L21/2855 ,  H01L21/28562 ,  H01L21/28568 ,  C23C14/18 ,  C23C16/14

Abstract: Embodiments of methods and associated apparatus for filling a feature in a substrate are provided herein. In some embodiments, a method of depositing tungsten in features of a substrate includes: depositing a seed layer consisting essentially of tungsten in the features via a physical vapor deposition (PVD) process; and depositing a bulk layer consisting essentially of tungsten in the features via a chemical vapor deposition (CVD) process to fill the features such that the deposition of the bulk layer is selective to within the features as compared to a field region of the substrate, wherein the CVD process is performed by flowing hydrogen gas (H2) at a first flow rate and a tungsten precursor at a second flow rate, and wherein the first flow rate is less than the second flow rate.

公开(公告)号：US20250006518A1

公开(公告)日：2025-01-02

申请号：US18753006

申请日：2024-06-25

Applicant: Applied Materials, Inc.

Inventor： Shiyu YUE ,  Wei LEI ,  Yu LEI ,  Ju Hyun OH ,  Zhimin QI ,  Sahil Jaykumar PATEL ,  Yi XU ,  Aixi ZHANG ,  Bingqian LIU ,  Cong TRINH ,  Xianmin TANG ,  Hayrensa ABLAT

IPC: H01L21/67 ,  H01L21/321 ,  H01L21/768 ,  H01L23/532

Abstract: Embodiments herein relate to a method, semiconductor device structures, and multi-chamber processing system for exposing a semiconductor device structure to an oxidizing plasma to form an oxide layer on at least one electrical connection formed in at least one feature formed within a dielectric layer of the semiconductor device structure, performing an etch process to remove the oxide layer and form an etch recess between a portion of the electrical connection and the dielectric layer At least a portion of the etch recess extends underneath at least a portion of the dielectric layer, and filling the at least one feature and the etch recess with a metal material.

公开(公告)号：US20240355673A1

公开(公告)日：2024-10-24

申请号：US18136970

申请日：2023-04-20

Applicant: Applied Materials, Inc.

Inventor： Wei LEI ,  Sahil PATEL ,  Yixiong YANG ,  Yu LEI ,  Shiyu YUE ,  Yi XU ,  Tuerxun AILIHUMAER ,  Juhyun OH ,  Xianmin TANG ,  Rongjun WANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53266 ,  C23C14/18 ,  H01L21/02063 ,  H01L21/28568

Abstract: Semiconductor devices and methods for molybdenum fill in semiconductor devices are provided. In one aspect, a method for processing a semiconductor device substrate is provided. The method includes exposing at least one feature formed in a dielectric layer to a grain modification layer deposition process to deposit a grain modification layer over at least a portion of the at least one feature. The at least one feature is defined by sidewall surfaces formed in the dielectric layer and a bottom surface extending between the sidewall surfaces. The method further includes exposing the at least one feature to a molybdenum deposition process to form a molybdenum-fill layer on the grain modification layer, wherein the grain modification layer comprises a metal different from molybdenum.

公开(公告)号：US20230343645A1

公开(公告)日：2023-10-26

申请号：US18128389

申请日：2023-03-30

Applicant: Applied Materials, Inc.

Inventor： Meng-Shan WU ,  Chih-Hsun HSU ,  Jiang LU ,  Shiyu YUE ,  Chun-chieh WANG ,  Annamalai LAKSHMANAN ,  Yixiong YANG

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76871 ,  H01L21/76843 ,  H01L23/53266 ,  H01L21/76865 ,  H01L21/76831

Abstract: A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on exposed top surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in the top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process removes the oxidized portion of the seed layer. A second etch process removes portions of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.

公开(公告)号：US20250157856A1

公开(公告)日：2025-05-15

申请号：US18912536

申请日：2024-10-10

Applicant: Applied Materials, Inc.

Inventor： Jiajie CEN ,  Zheng JU ,  Feng Q. LIU ,  Ying-Bing JIANG ,  Shiyu YUE ,  Xianmin TANG

IPC: H01L21/768 ,  C23C16/14 ,  C23C16/50

Abstract: Embodiments of the invention provide a method of forming a molybdenum (Mo) capping layer that is used to prevent copper diffusion in interconnect boundary regions of a formed semiconductor device. The molybdenum capping will improve copper boundary region properties to promote adhesion, decrease diffusion and copper agglomeration. Embodiments provide that a molybdenum capping layer may be selectively deposited on a surface of a copper interconnect structures formed in a dielectric layer formed on a substrate.

公开(公告)号：US20250079199A1

公开(公告)日：2025-03-06

申请号：US18458146

申请日：2023-08-29

Applicant: Applied Materials, Inc.

Inventor： Shiyu YUE ,  Sahil Jaykumar PATEL ,  Yu LEI ,  Wei LEI ,  Chih-Hsun HSU ,  Yi XU ,  Abulaiti HAIRISHA ,  Cong TRINH ,  Yixiong YANG ,  Ju Hyun OH ,  Aixi ZHANG ,  Xingyao GAO ,  Rongjun WANG

IPC: H01L21/67 ,  H01J37/32 ,  H01L21/3213

Abstract: A method of selective metal removal via gradient oxidation for a gap-fill includes performing process cycles, each process cycle including placing a wafer having a semiconductor structure thereon into a first processing station, the semiconductor structure including a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer, performing a reduction process on the wafer in the first processing station, performing a gradient oxidation process on the wafer in the second processing station, performing a gradient etch process on the wafer in the third processing station, and performing the gradient etch process on the wafer in the fourth processing station, wherein the first, second, third, and fourth processing stations are located in an interior volume of a processing chamber.

公开(公告)号：US20240420947A1

公开(公告)日：2024-12-19

申请号：US18210651

申请日：2023-06-16

Applicant: Applied Materials, Inc.

Inventor： Shiyu YUE ,  Jiajie CEN ,  Sahil Jaykumar PATEL ,  Zhimin QI ,  Ju Hyun OH ,  Aixi ZHANG ,  Xingyao GAO ,  Wei LEI ,  Yi XU ,  Yu LEI ,  Tsung-Han YANG ,  Xiaodong WANG ,  Xiangjin XIE ,  Yixiong YANG ,  Kevin KASHEFI ,  Rongjun WANG

IPC: H01L21/02 ,  H01L21/311

Abstract: A method of pre-cleaning in a semiconductor structure includes performing a plasma pre-treatment process to remove impurities from a surface of a semiconductor structure comprising a metal layer and a dielectric layer, performing a selective etch process to remove molybdenum oxide from a surface of the metal layer, the selective etch process comprising soaking the semiconductor structure in a precursor including molybdenum chloride (MoCl5, MoCl6) at a temperature of between 250° C. and 350° C., and performing a post-treatment process to remove chlorine residues and by-products of the selective etch process on the surface of the semiconductor structure.