公开(公告)号：US20080086664A1

公开(公告)日：2008-04-10

申请号：US11731392

申请日：2007-03-30

Applicant: Arash Behziz ,  Grady Borders

Inventor： Arash Behziz ,  Grady Borders

IPC: G01R31/28

CPC classification number: G01R31/31922 ,  G01R31/3191 ,  G01R31/31919 ,  G01R31/31937

Abstract: In one implementation, a method of testing multiple DUTs using a single tester channel is provided which includes providing an input signal with the single tester channel simultaneously to each of the DUTs. The method further includes providing a clock signal to each of the DUTs. The clock signal provided to each of the DUTs may be successively delayed clock signals, which are provided to successive DUTs. The method includes using the clock signal to cause a next DUTs to provide an output transition before an output of a prior DUT is returned to a pre-transition state. The method further includes detecting with the single tester channel the output transition of each of the DUTs in response to the input signal and the clock signal.

Abstract translation: 在一个实现中，提供了使用单个测试器通道来测试多个DUT的方法，其包括向每个DUT同时提供具有单个测试器通道的输入信号。 该方法还包括向每个DUT提供时钟信号。 提供给每个DUT的时钟信号可以是连续延迟的时钟信号，其提供给连续的DUT。 该方法包括使用时钟信号使得下一个DUT在先前DUT的输出返回到转换前状态之前提供输出转换。 该方法还包括响应于输入信号和时钟信号，用单个测试器通道检测每个DUT的输出转换。

公开(公告)号：US07890822B2

公开(公告)日：2011-02-15

申请号：US11731392

申请日：2007-03-30

Applicant: Arash Behziz ,  Grady Borders

Inventor： Arash Behziz ,  Grady Borders

IPC: G11C29/00 ,  G01R31/28 ,  G01R31/26

CPC classification number: G01R31/31922 ,  G01R31/3191 ,  G01R31/31919 ,  G01R31/31937

Abstract: In one implementation, a method of testing multiple DUTs using a single tester channel is provided which includes providing an input signal with the single tester channel simultaneously to each of the DUTs. The method further includes providing a clock signal to each of the DUTs. The clock signal provided to each of the DUTs may be successively delayed clock signals, which are provided to successive DUTs. The method includes using the clock signal to cause a next DUTs to provide an output transition before an output of a prior DUT is returned to a pre-transition state. The method further includes detecting with the single tester channel the output transition of each of the DUTs in response to the input signal and the clock signal.

Abstract translation: 在一个实现中，提供了使用单个测试器通道来测试多个DUT的方法，其包括向每个DUT同时提供具有单个测试器通道的输入信号。 该方法还包括向每个DUT提供时钟信号。 提供给每个DUT的时钟信号可以是连续延迟的时钟信号，其提供给连续的DUT。 该方法包括使用时钟信号使得下一个DUT在先前DUT的输出返回到转换前状态之前提供输出转换。 该方法还包括响应于输入信号和时钟信号，用单个测试器通道检测每个DUT的输出转换。

公开(公告)号：US20110280526A1

公开(公告)日：2011-11-17

申请号：US13016237

申请日：2011-01-28

Applicant: Arash Behziz ,  Arthur G. Buck

Inventor： Arash Behziz ,  Arthur G. Buck

IPC: G02B6/44 ,  H01B9/02

CPC classification number: H01B7/0009 ,  H01B7/04 ,  H01B7/423 ,  H01B11/1821 ,  H01B11/1891 ,  H01B11/22

Abstract: An electrical cable includes a central wire extending a length between opposite ends. The central wire has a periphery. Force wires have winding turns that are wrapped around the periphery of the central wire along the length of the central wire. The force wires include force conductors surrounded by force insulators. Return wires have winding turns that are wrapped around the periphery of the central wire along the length of the central wire. The return wires include return conductors surrounded by return insulators. The winding turns of the return wires are interleaved between the winding turns of adjacent force wires such that the adjacent force wires are separated by at least one return wire.

Abstract translation: 电缆包括在相对端之间延伸长度的中心线。 中心线具有外围。 电力线具有围绕中心线的周边沿着中心线的长度缠绕的绕组匝。 力线包括由力绝缘体包围的力导体。 回丝具有围绕中心线的周边沿着中心线的长度缠绕的绕组匝。 返回导线包括由返回绝缘体包围的返回导体。 返回线的绕组匝在相邻的力线的绕组匝之间交错，使得相邻的力线被至少一条回线隔开。

公开(公告)号：US07946853B2

公开(公告)日：2011-05-24

申请号：US11479205

申请日：2006-06-29

Applicant: Keith J. Breinlinger ,  Arash Behziz

Inventor： Keith J. Breinlinger ,  Arash Behziz

IPC: H01R12/00

CPC classification number: H01R13/2407 ,  G01R1/06772 ,  H01R12/714 ,  H01R12/75

Abstract: In one embodiment, a compliant contactor is provided which includes a center conductor and an outer conductor with a spacer therebetween. The outer conductor has a mating end adapted to be capable of flexibly contacting an outer conductor mating surface prior to the center conductor contacting a center conductor mating surface.

Abstract translation: 在一个实施例中，提供了柔性接触器，其包括中心导体和在其间具有间隔件的外导体。 外部导体具有匹配端，其适于在中心导体接触中心导体配合表面之前能够柔性地接触外部导体匹配表面。

公开(公告)号：US07492146B2

公开(公告)日：2009-02-17

申请号：US11266892

申请日：2005-11-03

Applicant: Arash Behziz

Inventor： Arash Behziz

IPC: G01R31/28

CPC classification number: H05K1/0251 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/116 ,  H05K2201/09718 ,  H05K2201/09727

Abstract: In one embodiment, a via structure for a printed circuit board is provided which includes a signal via and an elongated signal conductor strip electrically connected to the signal via. The elongated signal conductor strip is adjacent to a ground conductor and extends from the conductive pad substantially to the ground conductor. The elongated signal conductor strip includes a portion extending laterally outward, which may be configured to have a capacitance so as to establish an impedance for the via structure.

Abstract translation: 在一个实施例中，提供了一种用于印刷电路板的通孔结构，其包括电连接到信号通孔的信号通孔和细长的信号导体条。 细长的信号导体条与接地导体相邻并且从导电焊盘基本上延伸到接地导体。 细长信号导体条包括横向向外延伸的部分，其可以被配置为具有电容以便为通孔结构建立阻抗。

公开(公告)号：US20070007034A1

公开(公告)日：2007-01-11

申请号：US11474921

申请日：2006-06-26

Applicant: Arash Behziz ,  Roya Yaghmai

Inventor： Arash Behziz ,  Roya Yaghmai

IPC: H05K1/11 ,  H05K3/42

CPC classification number: H05K1/115 ,  G01R31/2889 ,  H05K3/3421 ,  H05K3/4602 ,  H05K2201/049 ,  H05K2201/09472 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09627 ,  H05K2201/10189 ,  Y10T29/49165

Abstract: In one embodiment, a laminated printed circuit board translator is provided. In some embodiments, the translator includes a receiving board adapted to receive a pin, the receiving board includes a plated via extending through the receiving board and has a hole for receiving a pin. An interface board laminated with the receiving board has a controlled depth via extending through it to contact a conductive trace. The conductive trace extends between the receiving board and the interface board to connect the plated via of the receiving board with the controlled depth via of the interface board. The controlled depth via is configured so that it is capable of being plated through a single sided drilled opening in the interface board. Some embodiments have a pad on the interface board connected to the controlled depth via.

Abstract translation: 在一个实施例中，提供了层压印刷电路板转换器。 在一些实施例中，翻译器包括适于接收销的接收板，接收板包括延伸穿过接收板的电镀通孔，并具有用于接收销的孔。 与接收板层压的接口板具有通过其延伸的受控深度以接触导电迹线。 导电迹线在接收板和接口板之间延伸，以将接收板的电镀通孔与接口板的受控深度通孔连接。 受控深度通孔被配置成能够通过接口板中的单面钻孔而进行电镀。 一些实施例在接口板上具有连接到受控深度通孔的垫。

公开(公告)号：US08696378B2

公开(公告)日：2014-04-15

申请号：US13404862

申请日：2012-02-24

Applicant: Arash Behziz ,  Dustin Grant Rowe

Inventor： Arash Behziz ,  Dustin Grant Rowe

IPC: H01R12/24

CPC classification number: H01R12/53 ,  H01R9/034 ,  H05K1/0218 ,  H05K1/117 ,  H05K3/325 ,  H05K2201/09618 ,  H05K2201/09845 ,  H05K2201/10356

Abstract: An electrical connector assembly including a printed circuit board that has base and cover layers of dielectric material and first and second ground planes of conductive material. The base and cover layers are stacked relative to each other and located between the first and second ground planes. The base layer has a conductor-receiving portion that extends beyond the cover layer. The circuit board also includes signal traces that are exposed to an open space that exists above the conductor-receiving portion. The connector assembly also includes a compression component that is configured to be positioned in the open space to press wire-terminating ends of signal conductors onto the signal traces at the conductor-receiving portion.

Abstract translation: 一种电连接器组件，包括具有介电材料的基底和覆盖层以及导电材料的第一和第二接地平面的印刷电路板。 底层和覆盖层相对于彼此堆叠并位于第一和第二接地平面之间。 基层具有延伸超过覆盖层的导体接收部分。 电路板还包括暴露于存在于导体接收部分之上的开放空间的信号迹线。 连接器组件还包括被配置为定位在开放空间中的压缩部件，以将信号导体的线端部按压到导体接收部分处的信号迹线上。

公开(公告)号：US08308491B2

公开(公告)日：2012-11-13

申请号：US13081000

申请日：2011-04-06

Applicant: Robert Paul Nichols ,  Brian Patrick Costello ,  Keith McQuilkin Murr ,  Arash Behziz ,  Scott D. Spicer ,  Richard Elof Hamner ,  Jason M'Cheyne Reisinger

Inventor： Robert Paul Nichols ,  Brian Patrick Costello ,  Keith McQuilkin Murr ,  Arash Behziz ,  Scott D. Spicer ,  Richard Elof Hamner ,  Jason M'Cheyne Reisinger

IPC: H01R12/00

CPC classification number: H01R12/73 ,  H01R24/40

Abstract: A connector assembly includes a connector housing configured to be coupled to a primary circuit board. A connector is held within the connector housing. The connector has a connector circuit board having a mating surface and a cable surface. The mating surface has mating contacts configured to be mated to corresponding mating contacts of a secondary circuit board. The cable surface has cable contacts. Cables extend between a first end and a second end. The first end of each cable is coupled to corresponding cable contacts of the connector circuit board. The second end of each cable is configured to be coupled to a cable contact on the primary circuit board or a second connector assembly on the primary circuit board.

Abstract translation: 连接器组件包括被配置为耦合到主电路板的连接器壳体。 连接器被保持在连接器壳体内。 连接器具有具有配合表面和电缆表面的连接器电路板。 配合表面具有被配置为与第二电路板的对应配合触点配合的配合触头。 电缆表面有电缆接触。 电缆在第一端和第二端之间延伸。 每个电缆的第一端连接到连接器电路板的相应电缆触头。 每个电缆的第二端被配置为耦合到主电路板上的电缆触点或主电路板上的第二连接器组件。

公开(公告)号：US07504822B2

公开(公告)日：2009-03-17

申请号：US11262001

申请日：2005-10-28

Applicant: Frank B. Parrish ,  Arash Behziz

Inventor： Frank B. Parrish ,  Arash Behziz

IPC: G01R31/02

CPC classification number: G01R31/2889 ,  G01R1/07378

Abstract: A device for interfacing a test head and a prober is disclosed using wires or cables to provide the connection from a probe card interface boards to the probe card. The use of wires or cables, in place of the traditional pogo pin arrangement allows for more reliable and efficient testing, as well as additional high performance tests to be run. Optionally, a probe interface contains a stiffening member with multiple sidewalks and individual, configuration-specific probe card interface strips are connected to a probe card through zero insertion force clamps. The probe card interface attaches to the test head using standard probe interface board (“PIB”) docking mechanics. The assembly is then connected to a probe to carry out the testing procedures.

Abstract translation: 使用电线或电缆公开了用于连接测试头和探测器的装置，以提供从探针卡接口板到探针卡的连接。 使用电线或电缆代替传统的pogo引脚布置，可以进行更可靠和高效的测试，以及进行额外的高性能测试。 可选地，探针接口包含具有多个人行道的加强构件，并且单独的配置专用探针卡接口条通过零插入力夹具连接到探针卡。 探头卡接口使用标准探头接口板（“PIB”）对接机构连接到测试头。 然后将组件连接到探头以执行测试程序。

公开(公告)号：US07180321B2

公开(公告)日：2007-02-20

申请号：US11235951

申请日：2005-09-27

Applicant: Arash Behziz ,  Keith Breinlinger ,  David Evans ,  Frank Parrish

Inventor： Arash Behziz ,  Keith Breinlinger ,  David Evans ,  Frank Parrish

IPC: G01R31/26

CPC classification number: H05K1/0243 ,  G01R31/2889 ,  H05K3/3447 ,  H05K3/368 ,  H05K2201/09809 ,  H05K2201/10356 ,  H05K2201/10666

Abstract: In one embodiment, a tester interface module for connecting a plurality of signal paths from at least one electronic assembly to at least one other electronic assembly is provided. The interface module includes a capture board having center conductor vias with center conductor holes extending through the capture board. Axial cables secured to the capture board have center conductors extending at least part way through a corresponding center conductor hole of the center conductor via. An interface component is adjacent to the capture board, the conductor paths being conductively bonded to the conductor vias of the capture board so as to electrically connect center conductors to corresponding conductor paths. The conductor paths of the interface component are arranged to allow connection with an electronic assembly.

Abstract translation: 在一个实施例中，提供了用于将多个信号路径从至少一个电子组件连接到至少一个其它电子组件的测试器接口模块。 接口模块包括具有中心导体通孔的捕获板，中心导体孔延伸穿过捕获板。 固定到捕获板的轴向电缆具有至少部分地延伸穿过中心导体通孔的相应中心导体孔的中心导体。 接口部件与捕获板相邻，导体路径导电地接合到捕获板的导体通孔，以将中心导体电连接到相应的导体路径。 接口部件的导体路径被布置成允许与电子组件的连接。