公开(公告)号：US20150052742A1

公开(公告)日：2015-02-26

申请号：US13973012

申请日：2013-08-22

Applicant: BOARDTEK ELECTRONICS CORPORATION

Inventor： CHIEN-CHENG LEE ,  Chung-Hsing Liao

IPC: H05K1/02

CPC classification number: H05K1/0204 ,  H05K1/021 ,  H05K3/0035 ,  H05K3/42 ,  H05K2201/10674 ,  H05K2203/025 ,  H05K2203/0597 ,  H05K2203/0733 ,  Y10T29/49124

Abstract: A circuit board structure manufacturing method includes the following steps. A circuit substrate is provided including an insulating layer, a first metal layer, and a second metal layer. The insulating layer is disposed between the first metal layer and the second metal layer. The first metal layer has a first cavity. The insulating layer has a second cavity and a provisional region. A width of the first cavity is larger than a width of the second cavity. The provisional region is defined between a sidewall of the first metal layer defining the first cavity and another sidewall of the first metal layer defining the second cavity. A first masking layer is formed to cover the first metal layer and provisional region. The second cavity is exposed from the first masking layer. A heat-dissipating metal member is formed in the second cavity. Furthermore, the first masking layer is removed.

Abstract translation: 电路板结构制造方法包括以下步骤。 提供了包括绝缘层，第一金属层和第二金属层的电路基板。 绝缘层设置在第一金属层和第二金属层之间。 第一金属层具有第一腔。 绝缘层具有第二腔和临时区。 第一腔的宽度大于第二腔的宽度。 临时区域限定在限定第一空腔的第一金属层的侧壁和限定第二空腔的第一金属层的另一个侧壁之间。 形成第一掩模层以覆盖第一金属层和临时区域。 第二腔从第一掩模层露出。 散热金属部件形成在第二腔中。 此外，去除第一掩模层。

公开(公告)号：US09271387B2

公开(公告)日：2016-02-23

申请号：US13973012

申请日：2013-08-22

Applicant: BOARDTEK ELECTRONICS CORPORATION

Inventor： Chien-Cheng Lee ,  Chung-Hsing Liao

IPC: H05K3/00 ,  H05K1/02 ,  H05K3/42

CPC classification number: H05K1/0204 ,  H05K1/021 ,  H05K3/0035 ,  H05K3/42 ,  H05K2201/10674 ,  H05K2203/025 ,  H05K2203/0597 ,  H05K2203/0733 ,  Y10T29/49124

Abstract: A circuit board structure manufacturing method includes the following steps. A circuit substrate is provided including an insulating layer, a first metal layer, and a second metal layer. The insulating layer is disposed between the first metal layer and the second metal layer. The first metal layer has a first cavity. The insulating layer has a second cavity and a provisional region. A width of the first cavity is larger than a width of the second cavity. The provisional region is defined between a sidewall of the first metal layer defining the first cavity and another sidewall of the first metal layer defining the second cavity. A first masking layer is formed to cover the first metal layer and provisional region. The second cavity is exposed from the first masking layer. A heat-dissipating metal member is formed in the second cavity. Furthermore, the first masking layer is removed.

Abstract translation: 电路板结构制造方法包括以下步骤。 提供了包括绝缘层，第一金属层和第二金属层的电路基板。 绝缘层设置在第一金属层和第二金属层之间。 第一金属层具有第一腔。 绝缘层具有第二腔和临时区。 第一腔的宽度大于第二腔的宽度。 临时区域限定在限定第一空腔的第一金属层的侧壁和限定第二空腔的第一金属层的另一个侧壁之间。 形成第一掩模层以覆盖第一金属层和临时区域。 第二腔从第一掩模层露出。 散热金属部件形成在第二腔中。 此外，去除第一掩模层。

公开(公告)号：US12074357B2

公开(公告)日：2024-08-27

申请号：US17389605

申请日：2021-07-30

Applicant: BOARDTEK ELECTRONICS CORPORATION

Inventor： Chung-Hsing Liao

IPC: H01P3/12 ,  H01P5/107 ,  H01Q9/04 ,  H05K1/02 ,  H05K1/18 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46

CPC classification number: H01P3/121 ,  H01P5/107 ,  H01Q9/045 ,  H05K1/0218 ,  H05K1/0298 ,  H05K1/18 ,  H05K3/243 ,  H05K3/429 ,  H05K3/4652 ,  H05K3/4664 ,  H05K3/4697 ,  H05K2201/0367 ,  H05K2201/0723 ,  H05K2201/09981 ,  H05K2201/09985 ,  H05K2201/10098 ,  H05K2201/10507 ,  H05K2203/0723

Abstract: An electromagnetic wave transmission board proofed against internal signal leakage includes an inner plate, a first outer plate, a second outer plate, a first plate bump, a first conductive bump, a second plate bump, and a second conductive bump. The inner plate defines a first through hole with a plated metal layer on the hole wall. The first and second plated bumps are disposed between the first outer and inner plates. The second plate bump and the second conductive bump are disposed between the second outer plate and the inner plate. The plate metal layer, the first plate bump, the first conductive bump, the first outer plate, the second outer plate, the second conductive bump, and the second plated bump jointly form an air-filled chamber. A method for manufacturing the electromagnetic wave transmission board is also provided.

公开(公告)号：US11129283B2

公开(公告)日：2021-09-21

申请号：US16356425

申请日：2019-03-18

Applicant: BOARDTEK ELECTRONICS CORPORATION

Inventor： Chien-Cheng Lee ,  Chung-Hsing Liao

IPC: H05K3/42 ,  H05K1/11

Abstract: An electroplating method of a circuit board includes: providing a multi-layer board having a conductive layer embedded therein; penetratingly forming a thru-hole and at least one penetrating hole in the multi-layer board, and forming a conductive portion on an inner wall defining the thru-hole and connected to the conductive layer, wherein the at least one penetrating hole is located at one side of the thru-hole, and an annular portion of the conductive layer exposed from the at least one penetrating hole is defined as an electroplated region; and electroplating the electroplated region to be formed with a metal post by applying a current to the conductive portion, wherein the metal post is filled in the at least one penetrating hole and is connected to the electroplated region.

公开(公告)号：US09860990B1

公开(公告)日：2018-01-02

申请号：US15393633

申请日：2016-12-29

Applicant: BOARDTEK ELECTRONICS CORPORATION

Inventor： Chien-Cheng Lee ,  Wen-Feng Cheng ,  Chung-Hsing Liao

IPC: H05K1/18 ,  H05K3/46 ,  H05K1/02 ,  H05K3/40 ,  H05K3/32 ,  H05K3/06 ,  H05K3/00

CPC classification number: H05K1/185 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/24247 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153 ,  H05K1/0203 ,  H05K1/0209 ,  H05K1/021 ,  H05K1/0268 ,  H05K1/0298 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/32 ,  H05K3/40 ,  H05K3/4641 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/066 ,  H05K2201/10522 ,  H05K2203/0228 ,  H05K2203/16

Abstract: A circuit board structure with chips embedded therein includes a multi-layer board and a power module embedded in the multi-layer board. The power module includes an insulating material, a power unit covered by the insulating material, and a circuit layer disposed on the insulating material. The power unit includes an electrically and thermally conductive carrier and a plurality of power chips. The electrically and thermally conductive carrier includes a transmitting portion and a carrying portion perpendicularly connected to the transmitting portion. Each power chip has a first electrode layer and an opposite second electrode layer. The first electrode layers are fixed on and electrically connected to the carrying portion in parallel, and the power chips are disposed at one side of the transmitting portion. The circuit layer is electrically connected to the electrically and thermally conductive carrier and the second electrode layers.