公开(公告)号：US20240194646A1

公开(公告)日：2024-06-13

申请号：US18374725

申请日：2023-09-29

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Lung-Hua Ho ,  Chih-Ming Kuo ,  Chen-Yu Wang ,  Chih-Hao Chiang ,  Pai-Sheng Cheng ,  Kung-An Lin ,  Chun-Ting Kuo ,  Yu-Hui Hu ,  Wen-Cheng Hsu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/13541 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/06517 ,  H01L2924/3511

Abstract: A semiconductor package includes a substrate, first bumps, a first chip, metal pillars, second bumps and a second chip. The substrate includes first and second conductive pads which are located on a top surface of the substrate. Both ends of the first bumps are connected to the first conductive pads and the first chip, respectively. Both ends of the metal pillars are connected to the second conductive pads and one end of the second bumps, respectively. A cross-sectional area of each of the metal pillars is larger than that of each of the second bumps. The second chip is connected to the other end of the second bumps and located above the first chip.

公开(公告)号：US20240105664A1

公开(公告)日：2024-03-28

申请号：US18234645

申请日：2023-08-16

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Yu-Chung Huang ,  Hsin-Yen Tsai ,  Fa-Chung Chen ,  Cheng-Fan Lin ,  Chen-Yu Wang

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L24/32 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/27 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/27515 ,  H01L2224/2784 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/3511

Abstract: A package structure includes a first RDL, an adhesive layer and a first electronic component. Upper bumps and conductive pads are provided on a first upper surface and a first lower surface of the first RDL, respectively. The adhesive layer is located on the first upper surface of the first RDL and surrounds the upper bumps. The first electronic component is mounted on the adhesive layer and includes conductors which are visible from an active surface of the first electronic component and joined to the upper bumps, the active surface of the first electronic component faces toward the first upper surface of the first RDL. Two adhesive surfaces of the adhesive layer are adhered to the first upper surface of the first RDL and the active surface of the first electronic component, respectively.

公开(公告)号：US20230420287A1

公开(公告)日：2023-12-28

申请号：US18137799

申请日：2023-04-21

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Ching-Wen Chen ,  Chen-Lung Teng ,  Kung-An Lin ,  Chen-Yu Wang

IPC: H01L21/687 ,  H01L21/67

CPC classification number: H01L21/68721 ,  H01L21/67092 ,  H01L21/68735

Abstract: A clamp assembly includes at least one clamp which is provided to clamp a workpiece in electroless plating, etching, electroplating or cleaning process. The clamp includes a base, a clamping element and a limiting element. The base is mounted on a carrier and includes a guide hole and a first limiting hole which are communicated with each other. The clamping element includes a guide rod and a second limiting hole, the guide rod is inserted into the guide hole to allow the second limiting hole located on the guide hole to be communicated with the first limiting hole. The limiting element is inserted into the first and second limiting holes to integrate the base with the clamping element for clamping the workpiece.

公开(公告)号：US20140097540A1

公开(公告)日：2014-04-10

申请号：US13677518

申请日：2012-11-15

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Hsiang-Chin Chiu ,  Sheng-Ming Wu ,  Kuang-Hao Yang ,  Kung-An Lin ,  Chen-Yu Wang

IPC: H01L23/373 ,  H01L23/482

CPC classification number: H01L23/3735 ,  H01L21/6836 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/4827 ,  H01L24/05 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05639 ,  H01L2924/10253

Abstract: A semiconductor structure includes a silicon substrate, a titanium layer, a nickel layer, a silver layer and a metallic adhesion layer, wherein the silicon substrate comprises a back surface, and the titanium layer comprises an upper surface. The titanium layer is formed on the back surface, the nickel layer is formed on the upper surface, the silver layer is formed on the nickel layer, and the metallic adhesion layer is formed between the nickel layer and the silver layer.

Abstract translation: 半导体结构包括硅衬底，钛层，镍层，银层和金属粘合层，其中硅衬底包括背面，并且钛层包括上表面。 钛层形成在背面，镍层形成在上表面，银层形成在镍层上，并且金属粘合层形成在镍层和银层之间。

公开(公告)号：US20240074127A1

公开(公告)日：2024-02-29

申请号：US18221461

申请日：2023-07-13

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chen-Yu Wang ,  Pai-Sheng Cheng ,  Huan-Kuen Chen

IPC: H05K9/00 ,  H05K1/05 ,  H05K1/18

CPC classification number: H05K9/0037 ,  H05K1/05 ,  H05K1/181 ,  H05K9/0088 ,  H05K2201/0104 ,  H05K2201/10977

Abstract: In a method of manufacturing an electronic package, first grooves are formed on a circuit structure and a second groove is formed in each of the first grooves to allow the circuit structure to become circuit layers. Owing to the second groove is narrower than the first groove, each of the circuit layers has an encircled surface and a notch located on the encircled surface. When a shielding layer is provided to cover an encapsulating body located on the circuit layer, a space of the notch is not covered by the shielding layer such that a portion to be removed of the shielding layer will not remain on the electronic package to become burr after removing the portion to be removed.

公开(公告)号：US20230135424A1

公开(公告)日：2023-05-04

申请号：US17896171

申请日：2022-08-26

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Shrane-Ning Jenq ,  Wen-Cheng Hsu ,  Chen-Yu Wang ,  Chih-Ming Kuo ,  Chwan-Tyaw Chen ,  Lung-Hua Ho

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/311 ,  H01L21/3213 ,  C23C18/54 ,  C23C28/02 ,  C25D7/12

Abstract: A package including a first carrier, a seed layer, wires, a die and a molding material is provided. The first carrier is removed to expose the seed layer after disposing a second carrier on the molding material, then the seed layer is removed to expose the wires, and a gold layer is deposited on each of the wires by immersion gold plating, finally a semiconductor device is obtained. The gold layer is provided to protect the wires from oxidation and improve solder joint reliability.

公开(公告)号：US12224183B2

公开(公告)日：2025-02-11

申请号：US17896171

申请日：2022-08-26

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Shrane-Ning Jenq ,  Wen-Cheng Hsu ,  Chen-Yu Wang ,  Chih-Ming Kuo ,  Chwan-Tyaw Chen ,  Lung-Hua Ho

IPC: H01L21/48 ,  C23C18/54 ,  C23C28/02 ,  C25D7/12 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/498 ,  H01L23/00

Abstract: A package including a first carrier, a seed layer, wires, a die and a molding material is provided. The first carrier is removed to expose the seed layer after disposing a second carrier on the molding material, then the seed layer is removed to expose the wires, and a gold layer is deposited on each of the wires by immersion gold plating, finally a semiconductor device is obtained. The gold layer is provided to protect the wires from oxidation and improve solder joint reliability.

公开(公告)号：US20230378044A1

公开(公告)日：2023-11-23

申请号：US18109337

申请日：2023-02-14

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Lung-Hua Ho ,  Chih-Ming Kuo ,  Chun-Ting Kuo ,  Yu-Hui Hu ,  Chih-Hao Chiang ,  Chen-Yu Wang ,  Kung-An Lin ,  Pai-Sheng Cheng

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13014 ,  H01L2224/16227

Abstract: A flip-chip bonding structure includes a substrate and a chip. A lead of the substrate includes a body, a hollow opening, a bonding island and at least one connecting bridge. The hollow opening is in the body and surrounded by the body. The bonding island is located in the hollow opening such that there is a hollow space in the hollow opening and located between the body and the bonding island. The connecting bridge is located in the hollow space to connect the body and the bonding island. A bump of the chip is bonded to the bonding island by a solder. The solder is restricted on the bonding island and separated from the body by the hollow space so as to avoid the solder from overflowing to the body and avoid the chip from shifting.

公开(公告)号：US20230187378A1

公开(公告)日：2023-06-15

申请号：US17988846

申请日：2022-11-17

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Shrane-Ning Jenq ,  Chen-Yu Wang ,  Chin-Tang Hsieh ,  Shu-Yeh Chang ,  Lung-Hua Ho

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L23/3121 ,  H01L23/49811 ,  H01L21/561

Abstract: In a method of manufacturing a semiconductor package, at least one conductive wire is formed on a substrate in a wire bonding process, a ball end of the conductive wire is located above the substrate, a molding material is provided to cover the conductive wire except the ball end, and an EMI shielding layer is formed on the molding material to connect to the ball end. Owing to the ball end is exposed on the molding material, connection area of the EMI shielding layer to the conductive wire is increased to improve connection strength and reliability between the EMI shielding layer and the conductive wire.