公开(公告)号：US20240291497A1

公开(公告)日：2024-08-29

申请号：US18584706

申请日：2024-02-22

Applicant: Daegu Gyeongbuk Institute of Science and Technology

Inventor： Jung Hyup LEE ,  Geun Ha Kim ,  Jae Eun Jang

IPC: H03M1/08

CPC classification number: H03M1/08

Abstract: The present invention relates to a successive approximation register (SAR) analog-to-digital converter and the SAR analog-to-digital converter according to an example embodiment includes an input unit including at least one SAR capacitor; a recycling integrator connected to the input unit and including k integration capacitors configured to store the respective residue information generated in an integration process performed k times, respectively, (where k denotes a positive integer of 2 or more) using a single amplifier; a comparator connected to an output terminal of the recycling integrator; and a SAR controller connected to an output terminal of the comparator and configured to generate a digital signal corresponding to output of the comparator.

公开(公告)号：US20240291500A1

公开(公告)日：2024-08-29

申请号：US18584598

申请日：2024-02-22

Applicant: Daegu Gyeongbuk Institute of Science and Technology

Inventor： Jung Hyup LEE ,  Tae Ryoung SEOL ,  Ji Woong CHOI

IPC: H03M1/48 ,  H03M1/46

CPC classification number: H03M1/48 ,  H03M1/46

Abstract: The present invention relates to a current-to-digital converter and the current-to-digital converter according to an example embodiment includes an integrator connected to a current source that outputs input current; a quantizer connected to the integrator and configured to generate a first digital output code corresponding to alternating current (AC) in the input current; a first loop circuit formed on a delta-sigma (ΔΣ) loop that connects an input terminal of the integrator and an output terminal of the quantizer; a second loop circuit formed on a truncation-noise-shaped baseline-servo (TNS-BS) loop that connects the input terminal of the integrator and the output terminal of the quantizer and configured to generate a second digital output code corresponding to direct current (DC) in the input current; and an adder configured to generate a final digital output code by adding the first digital output code and the second digital output code.

公开(公告)号：US20180219536A1

公开(公告)日：2018-08-02

申请号：US15881232

申请日：2018-01-26

Applicant: Daegu Gyeongbuk Institute of Science and Technology

Inventor： Jung Hyup LEE ,  Kocheethra George ARUP ,  Minkyu JE

IPC: H03K4/501 ,  H03K3/011 ,  H03K3/0231 ,  G06F1/04 ,  G06F1/32

CPC classification number: H03K4/501 ,  G06F1/04 ,  G06F1/32 ,  H03K3/011 ,  H03K3/012 ,  H03K3/013 ,  H03K3/0231

Abstract: Disclosed is a differential relaxation oscillator using a differential structure that may stably maintain a differential voltage swing of capacitors despite an influence of an offset voltage and 1/f noise of a comparator, and also generate a dynamic current only at a point in time at which switching is performed, thereby minimizing power consumption.

公开(公告)号：US20230261671A1

公开(公告)日：2023-08-17

申请号：US18168882

申请日：2023-02-14

Applicant: Daegu Gyeongbuk Institute of Science and Technology

Inventor： Jung Hyup LEE ,  Ji Woong CHOI ,  Se Hwan LEE

IPC: H03M3/00

CPC classification number: H03M3/484

Abstract: Disclosed are a continuous-time delta-sigma analog-to-digital converter and an operation method thereof. More particularly, a continuous-time delta-sigma analog-to-digital converter, including: a linear integrator configured to generate a first output signal corresponding to a preset input voltage based on an operation of a linear Gm circuit that receives the preset input voltage; and a quantizer configured to generate a second output signal corresponding to the first output signal based on an operation of a body-driven VCO that receives the first output signal and to generate a digital output code corresponding to the second output signal based on an operation of a Frequency to Digital Converter (FDC) that receives the second output signal is disclosed.

公开(公告)号：US20230261670A1

公开(公告)日：2023-08-17

申请号：US18170228

申请日：2023-02-16

Applicant: Daegu Gyeongbuk Institute of Science and Technology

Inventor： Jung Hyup LEE ,  Se Hwan Lee

IPC: H03M3/00

CPC classification number: H03M3/458

Abstract: Disclosed is an input impedance boosting apparatus. More particularly, an input impedance boosting apparatus including an analog-to-digital converter; an input capacitor connected to an input terminal of the analog-to-digital converter and a ground line and including a first shielding metal formed thereunder; a feedback capacitor connected onto a positive feedback loop of the analog-to-digital converter and including a second shielding metal formed thereunder; and an impedance booster connected to both ends of the feedback capacitor and configured to boost an input impedance based on a first parasitic component formed between the input capacitor and the first shielding metal and a second parasitic component formed between the feedback capacitor and the second shielding metal is provided.