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公开(公告)号：US20250110173A1
公开(公告)日：2025-04-03
申请号：US18477360
申请日：2023-09-28
Applicant: Intel Corporation
Inventor： Gregorio R. Murtagian
Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed that improve thermal tests of integrated circuit devices. An example apparatus includes interface circuitry; machine readable instructions; and programmable circuitry to at least one of instantiate or execute the machine readable instructions to determine a condition of a fluid to be dispensed by a pneumatic nozzle, the condition of the fluid including a temperature of the fluid; determine a ratio of a first liquid, a second liquid, and a superheated vapor that combine to result in the condition of the fluid; and cause the first liquid, the second liquid, and the superheated vapor to be provided to the pneumatic nozzle in proportions defined by the ratio.
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公开(公告)号：US09692147B1
公开(公告)日：2017-06-27
申请号：US14979037
申请日：2015-12-22
Applicant: Intel Corporation
Inventor： Srikant Nekkanty , Donald T. Tran , Gregorio R. Murtagian
CPC classification number: H01R4/58 , H01R12/52 , H01R12/718 , H01R12/73 , H05K5/0086
Abstract: An electronic device connection system includes a first electrical device and a second electrical device. The first electrical device includes a plurality of electrical connectors disposed in, on, or about at least a portion of an exterior surface of the first electrical device. The second electrical device includes a plurality of electrical contacts disposed in, on, or about at least a portion of an exterior surface of the second electrical device. A mechanical compressor exerts a force on at least one of the first electrical device or the second electrical device such that the electrical connections on the first electrical device physically and conductively couple to the electrical contacts on the second electrical device. The device casing may function as the mechanical compressor. The electrical connectors and/or electrical contacts may include injection molded connectors that include a conductive material dispersed in a thermoplastic matrix.
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公开(公告)号：US12174436B2
公开(公告)日：2024-12-24
申请号：US17214035
申请日：2021-03-26
Applicant: Intel Corporation
Inventor： Wesley Morgan , Srikant Nekkanty , Todd R. Coons , Gregorio R. Murtagian , Xiaoqian Li , Nitin Deshpande , Divya Pratap
Abstract: Embodiments disclosed herein include photonics packages and systems. In an embodiment, a photonics package comprises a package substrate, where the package substrate comprises a cutout along an edge of the package substrate. In an embodiment, a photonics die is coupled to the package substrate, and the photonics die is positioned adjacent to the cutout. In an embodiment, the photonics package further comprises a receptacle for receiving a pluggable optical connector. In an embodiment, the receptacle is over the cutout.
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公开(公告)号：US20200335432A1
公开(公告)日：2020-10-22
申请号：US16388136
申请日：2019-04-18
Applicant: Intel Corporation
Inventor： Gregorio R. Murtagian , Jeffory L. Smalley , Thomas T. Holden , Silver A. Estrada Rodriguez , Luis E. Rosales Galvan
IPC: H01L23/498 , H01L21/67 , H05K1/18
Abstract: A circuit board assembly includes at least one circuit board having a plurality of conductive layers, the at least one circuit board having a first face and an opposite second face. A first chip socket on the first face is positioned opposite of a second chip socket on the second face. In one example, each chip socket can receive a processor. The first and second chip sockets may be arranged in a mirrored fashion with respect to one another, or an overlapping but non-mirrored fashion. In any such arrangements, as fasteners are tightened to fully seat first and second chips respectively installed in the first and second chip sockets, forces applied to the first chip effectively neutralize or otherwise reduce opposing forces applied to the second chip, thereby reducing circuit board deflection.
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公开(公告)号：US09461431B2
公开(公告)日：2016-10-04
申请号：US14751871
申请日：2015-06-26
Applicant: INTEL CORPORATION
Inventor： Gregorio R. Murtagian , Bhanu Jaiswal , Sriram Srinivasan , Michael J. Hill
CPC classification number: H01R43/205 , H01R12/73 , H01R13/6205 , H01R43/26 , Y10T29/4913 , Y10T29/49146 , Y10T29/49149
Abstract: A mechanism is described for facilitating and employing a magnetic grid array according to one embodiment. A method of embodiments may include engaging, via magnetic force of a magnet, magnetic contacts of a magnetic grid array to substrate lands of a package substrate of an integrated circuit package of a computing system, and disengaging, via a removal lever, the magnetic contacts from the substrate lands.
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Patent Agency Ranking
公开(公告)号：US12207398B2
公开(公告)日：2025-01-21
申请号：US17664408
申请日：2022-05-21
Applicant: Georgia Tech Research Corporation , Intel Corporation
Inventor： Omkar Gupte , Vanessa Smet , Gregorio R. Murtagian
Abstract: An electronic device carrier structure can include a substrate including a plurality of electrical contacts spaced apart on the substrate, a plurality of electrically conductive balls, each of the electrically conductive balls being on a respective one of the plurality of electrical contacts, solder attaching each of the electrically conductive balls to respective ones of the electrical contacts to form an attachment boundary where the solder ends on a surface of each of the plurality of electrically conductive balls, and a polymer layer extending on the substrate onto the plurality of electrically conductive balls to form a surface of the polymer layer at a contact point on the plurality of electrically conductive balls that is above the attachment boundary and below an apex of each of the plurality of electrically conductive balls.
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公开(公告)号：US20220386457A1
公开(公告)日：2022-12-01
申请号：US17664408
申请日：2022-05-21
Applicant: Georgia Tech Research Corporation , Intel Corporation
Inventor： Omkar Gupte , Vanessa Smet , Gregorio R. Murtagian
Abstract: An electronic device carrier structure can include a substrate including a plurality of electrical contacts spaced apart on the substrate, a plurality of electrically conductive balls, each of the electrically conductive balls being on a respective one of the plurality of electrical contacts, solder attaching each of the electrically conductive balls to respective ones of the electrical contacts to form an attachment boundary where the solder ends on a surface of each of the plurality of electrically conductive balls, and a polymer layer extending on the substrate onto the plurality of electrically conductive balls to form a surface of the polymer layer at a contact point on the plurality of electrically conductive balls that is above the attachment boundary and below an apex of each of the plurality of electrically conductive balls.
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公开(公告)号：US11291133B2
公开(公告)日：2022-03-29
申请号：US15938980
申请日：2018-03-28
Applicant: Intel Corporation
Inventor： Zhichao Zhang , Gregorio R. Murtagian , Kuang C Liu , Kemal Aygun
Abstract: Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.
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公开(公告)号：US10396036B2
公开(公告)日：2019-08-27
申请号：US15774257
申请日：2015-12-26
Applicant: Intel Corporation
Inventor： Yu Amos Zhang , Zhiguo Qian , Kemal Aygun , Yidnekachew S. Mekonnen , Gregorio R. Murtagian , Sanka Ganesan , Eduard Roytman , Jeff C. Morriss
IPC: H01L23/48 , H01L23/538 , H01L23/552 , H01L23/66 , H01L23/498 , H01L23/50 , H01L25/065
Abstract: A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia). The ground shielding for the electro-optical module may include patterns of ground isolation shielding attachments and contacts.
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公开(公告)号：US09832876B2
公开(公告)日：2017-11-28
申请号：US14575775
申请日：2014-12-18
Applicant: INTEL CORPORATION
Inventor： Mani Prakash , Thomas T. Holden , Jeffory L. Smalley , Ram S. Viswanath , Bassam N. Coury , Dimitrios Ziakas , Chong J. Zhao , Jonathan W. Thibado , Gregorio R. Murtagian , Kuang C. Liu , Rajasekaran Swaminathan , Zhichao Zhang , John M. Lynch , David J. Llapitan , Sanka Ganesan , Xiang Li , George Vergis
CPC classification number: H05K1/181 , H01L23/00 , H01L23/498 , H01L2224/16225 , H01L2924/15311 , H01R12/712 , H01R12/79 , H05K2201/10159 , H05K2201/10325 , Y02P70/611
Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
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