公开(公告)号：US20200335432A1

公开(公告)日：2020-10-22

申请号：US16388136

申请日：2019-04-18

Applicant: Intel Corporation

Inventor： Gregorio R. Murtagian ,  Jeffory L. Smalley ,  Thomas T. Holden ,  Silver A. Estrada Rodriguez ,  Luis E. Rosales Galvan

IPC: H01L23/498 ,  H01L21/67 ,  H05K1/18

Abstract: A circuit board assembly includes at least one circuit board having a plurality of conductive layers, the at least one circuit board having a first face and an opposite second face. A first chip socket on the first face is positioned opposite of a second chip socket on the second face. In one example, each chip socket can receive a processor. The first and second chip sockets may be arranged in a mirrored fashion with respect to one another, or an overlapping but non-mirrored fashion. In any such arrangements, as fasteners are tightened to fully seat first and second chips respectively installed in the first and second chip sockets, forces applied to the first chip effectively neutralize or otherwise reduce opposing forces applied to the second chip, thereby reducing circuit board deflection.

公开(公告)号：US20180007791A1

公开(公告)日：2018-01-04

申请号：US15702709

申请日：2017-09-12

Applicant: Intel Corporation

Inventor： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

IPC: H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H01R12/71 ,  H01R12/79

CPC classification number: H05K1/181 ,  H01L23/00 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/712 ,  H01R12/79 ,  H05K2201/10159 ,  H05K2201/10325 ,  Y02P70/611

Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.

公开(公告)号：US20190141845A1

公开(公告)日：2019-05-09

申请号：US16220631

申请日：2018-12-14

Applicant: Intel Corporation

Inventor： Mani Prakash ,  Thomas T. Holden ,  Aaron Gorius ,  Michael T. Crocker ,  Matthew J. Adiletta ,  Russell Aoki

IPC: H05K5/00 ,  H05K5/02 ,  H05K7/02

Abstract: A configurable processor module includes a central processing unit (CPU) package mounted to a CPU substrate, which may be mounted to a circuit board substrate. The CPU substrate may include physical resources usable by the CPU package, which may not be included or duplicated on the circuit board substrate. As such, features of the CPU package that are unavailable on the circuit board substrate may be available on the CPU substrate. Additionally, the CPU substrate and physical resources may be selected and designed so as to provide varying levels of functionality across different compute devices that use the same type of CPU package.

公开(公告)号：US09832876B2

公开(公告)日：2017-11-28

申请号：US14575775

申请日：2014-12-18

Applicant: INTEL CORPORATION

Inventor： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

IPC: H05K1/18 ,  H01L23/00 ,  H01R12/71 ,  H01R12/79

CPC classification number: H05K1/181 ,  H01L23/00 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/712 ,  H01R12/79 ,  H05K2201/10159 ,  H05K2201/10325 ,  Y02P70/611

Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.