公开(公告)号：US20170186661A1

公开(公告)日：2017-06-29

申请号：US14998123

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： Russell S. Aoki ,  Jonathan W. Thibado ,  Jeffory L. Smalley ,  David J. Llapitan ,  Thomas A. Boyd ,  Harvey R. Kofstad ,  Dimitrios Ziakas ,  Hongfei Yan

IPC: H01L23/34 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H01L23/498

CPC classification number: H01L23/345 ,  H01L23/4006 ,  H01L23/49816 ,  H01L23/49822 ,  H05K1/0212 ,  H05K1/141 ,  H05K1/144 ,  H05K3/3436 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2203/176

Abstract: A rework grid array interposer with direct power is described. The interposer has a foundation layer mountable between a motherboard and a package. A heater is embedded in the foundation layer to provide local heat to reflow solder to enable at least one of attachment or detachment of the package. A connector is mounted on the foundation layer and coupled to the heater and to the package to provide a connection path directly with the power supply and not via the motherboard. One type of interposer interfaces with a package having a solderable extension. Another interposer has a plurality of heater zones embedded in the foundation layer.

公开(公告)号：US09603276B2

公开(公告)日：2017-03-21

申请号：US14583372

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： David J. Llapitan ,  Jeffory L. Smalley ,  Gaurav Chawla ,  Joshua D Heppner ,  Vijaykumar Krithivasan ,  Jonathan W. Thibado ,  Kuang Liu ,  Gregorio Murtagian

IPC: H01R12/00 ,  H05K7/10

CPC classification number: H05K7/1084

Abstract: Some forms relate to an electronic assembly that includes a plurality of electronic package. The electronic assembly includes a frame and a first electronic package mounted on the frame. The first electronic package includes a first pin grid array. The electronic assembly further includes a second electronic package mounted on the frame. The second electronic package includes a second pin grid array. The electronic assembly further includes an actuation mechanism on the frame. The actuation mechanism is configured to move the first electronic package and the second electronic package relative to the frame during operation of the actuation mechanism.

公开(公告)号：US12219706B2

公开(公告)日：2025-02-04

申请号：US17354989

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Jonathan W. Thibado ,  Aaron Gorius ,  Michael T. Crocker ,  Matthew J. Adiletta ,  John C. Gulick ,  Emery E. Frey

IPC: H05K1/00 ,  H05K1/03 ,  H05K1/11 ,  H05K3/28 ,  H05K3/36 ,  H05K7/02 ,  H05K7/20

Abstract: Examples described herein relate to an apparatus that includes a flexible conductor covered in an insulative material and at least one conductor region in contact with the flexible conductor. In some examples, melting of the at least one conductor region is to cause a conductive coupling of the flexible conductor with a second conductor and wherein the flexible conductor is adapted to conductively couple a first circuit board oriented orthogonal to a second circuit board. In some examples, the at least one conductor region comprises at least one solder ball of a grid array. In some examples, the at least one conductor region is re-solderable.

公开(公告)号：US20170354031A1

公开(公告)日：2017-12-07

申请号：US15172102

申请日：2016-06-02

Applicant: Intel Corporation

Inventor： Russell S. Aoki ,  Jeffory L. Smalley ,  Jonathan W. Thibado

IPC: H05K1/02 ,  H01L23/00 ,  H01L25/065 ,  H05K1/14 ,  H05K3/36 ,  H05K1/18 ,  H05K3/34 ,  H01L23/498 ,  G06F1/16

CPC classification number: H05K1/0271 ,  G06F1/16 ,  G06F1/206 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15323 ,  H05K1/0212 ,  H05K1/144 ,  H05K1/181 ,  H05K3/341 ,  H05K3/3436 ,  H05K3/3494 ,  H05K3/368 ,  H05K2201/041 ,  H05K2201/10189 ,  H05K2201/10325 ,  H05K2201/10378 ,  H05K2201/10409 ,  H05K2201/10734

Abstract: An apparatus is provided which comprises: a processor die; a processor substrate having a region extended away from the processor die, wherein the processor die is mounted on the processor substrate, wherein the extended region has at least one signal interface which is connectable to a top-side connector; and an interposer coupled to the processor substrate and a motherboard.

公开(公告)号：US12082370B2

公开(公告)日：2024-09-03

申请号：US17337342

申请日：2021-06-02

Applicant: Intel Corporation

Inventor： Aaron Gorius ,  Michael T. Crocker ,  Jonathan W. Thibado ,  Matthew J. Adiletta ,  John C. Gulick ,  Emery E. Frey

IPC: H05K7/20

CPC classification number: H05K7/20272 ,  H05K7/20236 ,  H05K7/20281 ,  H05K7/205

Abstract: Examples described herein relate to a system. The system can include a container that contains fluid to provide two phase immersion liquid cooling (2PILC) for a system within the container. The container can enclose a first circuit board with a first side of the first circuit board is conductively coupled to at least one device. The container can enclose a motherboard conductively coupled to a second side of the first circuit board with a first side of the motherboard is conductively coupled to the second side of the first circuit board. The motherboard can include at least four edges. Connectors can conductively connect the motherboard with a second circuit board. The second circuit board can include at least four edges and an edge of the motherboard is oriented approximately 90 degrees to an edge of the second circuit board. At least one device can include one or more of: a processor, memory device, accelerator device, or network interface.

公开(公告)号：US11683890B2

公开(公告)日：2023-06-20

申请号：US16227243

申请日：2018-12-20

Applicant: INTEL CORPORATION

Inventor： Jonathan W. Thibado ,  Jeffory L. Smalley ,  John C. Gulick ,  Phi Thanh ,  Mohanraj Prabhugoud

IPC: H05K3/34 ,  H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  G06F1/16 ,  H01L23/498

CPC classification number: H05K3/3494 ,  G06F1/16 ,  H01L23/49816 ,  H05K1/0201 ,  H05K1/0212 ,  H05K1/112 ,  H05K1/181 ,  H05K3/3421 ,  H05K2201/10053 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: A reflowable grid array (RGA) interposer includes first connection pads on a first surface of a body and second connection pads on a second surface of the body. Heating elements within the body are adjacent to the second connection pads. First interconnects within the body connect some of the second connection pads to the first connection pads. Second interconnects within the body connect pairs of the second connection pads. A motherboard assembly includes first and second components (e.g., CPU with co-processor and/or memory) and the RGA interposer. The first connection pads are in contact with motherboard contacts. The second connection pads are in contact with the first and second components. The first component passes signals directly to the motherboard by the first interconnects. The second component passes signals directly to the first component by the second interconnects but does not pass signals directly to the motherboard by the first interconnects.

公开(公告)号：US11488839B2

公开(公告)日：2022-11-01

申请号：US16249512

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Jonathan W. Thibado ,  Jeffory L. Smalley ,  John C. Gulick ,  Phi Thanh

IPC: H01L21/48 ,  H05K3/34 ,  H01L23/36 ,  H01L23/498 ,  H01L21/50 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H01L23/58

Abstract: Embodiments include a reflowable grid array (RGA) interposer, a semiconductor packaged system, and a method of forming the semiconductor packaged system. The RGA interposer includes a plurality of heater traces in a substrate. The RGA interposer also includes a plurality of vias in the substrate. The vias extend vertically from the bottom surface to the top surface of the substrate. The RGA interposer may have one of the vias between two of the heater traces, wherein the vias have a z-height that is greater than a z-height of the heater traces. The heater traces may be embedded in a layer of the substrate, where the layer of the substrate is between top ends and bottom ends of the vias. Each of the plurality of heater traces may include a via filament interconnect coupled to a power source and a ground source. The heater traces may be resistive heaters.

公开(公告)号：US11621237B2

公开(公告)日：2023-04-04

申请号：US16247312

申请日：2019-01-14

Applicant: Intel Corporation

Inventor： Jonathan W. Thibado ,  Jeffory L. Smalley ,  John C. Gulick ,  Phi Thanh ,  Mohanraj Prabhugoud ,  Chong Zhao

IPC: H05K1/02 ,  H01L23/66 ,  H01L23/498 ,  H01L23/34 ,  H01B7/04 ,  G02B6/42 ,  H01B3/30 ,  H01B7/08 ,  H01L25/10 ,  H05K1/18

Abstract: Embodiments include interposers for use in high speed applications. In an embodiment, the interposer comprises an interposer substrate, and an array of pads on a first surface of the interposer substrate. In an embodiment, a plurality of vias pass through the interposer substrate, where each via is electrically coupled to one of the pads in the array of pads. In an embodiment a plurality of heating elements are embedded in the interposer substrate. In an embodiment a first cable is over the first surface interposer substrate. In an embodiment, the first cable comprises an array of conductive lines along the first cable, where conductive lines proximate to a first end of the cable are electrically coupled to pads in the array of pads.

公开(公告)号：US20180352649A1

公开(公告)日：2018-12-06

申请号：US15777860

申请日：2016-06-02

Applicant: Intel Corporation

Inventor： Russell S. Aoki ,  Jeffory L. Smalley ,  Jonathan W. Thibado

IPC: H05K1/02 ,  B23K1/00 ,  H01L23/498 ,  H05B1/02 ,  H05K1/14 ,  B23K101/42

CPC classification number: H05K1/0271 ,  B23K1/0016 ,  B23K2101/42 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05B1/0233 ,  H05K1/0212 ,  H05K1/141 ,  H05K2201/041 ,  H05K2201/10378

Abstract: An apparatus is provided which comprises: a processor substrate extended away from a processor die, wherein the processor substrate has at least one signal interface which is connectable to a connector; and an interposer coupled to the processor substrate and a motherboard. Described is an apparatus which comprises: a processor substrate extended away from a processor die, wherein the processor substrate has at least one signal interface; and a motherboard coupled to the processor substrate, wherein the motherboard is configured to have a hole which is large enough to place a connector at least partially in it to couple with the at least one signal interface.

公开(公告)号：US20180007791A1

公开(公告)日：2018-01-04

申请号：US15702709

申请日：2017-09-12

Applicant: Intel Corporation

Inventor： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

IPC: H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H01R12/71 ,  H01R12/79

CPC classification number: H05K1/181 ,  H01L23/00 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/712 ,  H01R12/79 ,  H05K2201/10159 ,  H05K2201/10325 ,  Y02P70/611

Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.