公开(公告)号：US20210119044A1

公开(公告)日：2021-04-22

申请号：US15439951

申请日：2017-02-23

Applicant: Indian Institute of Science

Inventor： Mayank SHRIVASTAVA

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092

Abstract: A Drain Extended Tunnel FET (DeTFET) device is disclosed that outperforms state of art devices and can meet the requirements of High voltage/high power devices operating in the range of 5V-20V for System on Chip (SoC). The device comprises a P+ SiGe source with an N-type Si Epilayer sandwiched between SiGe source and the gate stack, which enables vertical tunneling of minority carriers from SiGe P+ source into N-Epi region under the influence of gate field. The area tunneling between SiGe source and Si Epi region breaks the barrier imposed by thermionic injection based carrier transport from source to channel, which exists in DeMOS devices known in the art. The disclosed device results in improved performance in respect of ON current, leakage, sub-threshold slope, breakdown voltage and RF characteristics making it attractive for SoC applications as compared to its state of the art counterparts.

公开(公告)号：US20200227543A1

公开(公告)日：2020-07-16

申请号：US16629156

申请日：2018-07-06

Applicant: Indian Institute of Science

Inventor： Rohith SOMAN ,  Ankit SONI ,  Mayank SHRIVASTAVA ,  Srinivasan RAGHAVAN ,  Navakant BHAT

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423

Abstract: A High Electron Mobility Transistor (HEMT) having a reduced surface field (RESURF) junction is provided. The HEMT includes a source electrode at a first end and a drain electrode at a second end. A gate electrode is provided between the source electrode and the drain electrode. A reduced surface field (RESURF) junction extends from the first end to the second end. The gate electrode is provided above the RESURF junction. A buried channel layer is formed in the RESURF junction on application of a positive voltage at the gate electrode. The RESURF junction includes an n-type Gallium nitride (GaN) layer and a p-type GaN layer. The n-type GaN layer is provided between the p-type GaN layer and the gate electrode.

公开(公告)号：US20180219007A1

公开(公告)日：2018-08-02

申请号：US15883591

申请日：2018-01-30

Applicant: INDIAN INSTITUTE OF SCIENCE

Inventor： Mayank SHRIVASTAVA ,  Milova PAUL ,  Christian RUSS ,  Harald GOSSNER

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L27/0296 ,  H01L29/742 ,  H01L29/7436 ,  H01L29/785

Abstract: The present disclosure relates to a Silicon Controlled Rectifier (SCR) in non-planar technology to provide a robust ESD protection in System on Chip employing non-planar technologies. The disclosed SCR incorporates wire or fin shaped nanostructures extending from p-type tap to cathode, from the cathode to anode, and from the anode to n-type tap to provide parallel trigger paths to prevent problem of current crowding at the base emitter junction that limits efficient turn-on in conventional SCRs. The proposed structure helps in offering lower trigger and holding voltage, and therefore very high failure currents. The disclosed SCR has sub-3V trigger and holding voltage to provide an efficient and robust ESD protection in SOCs. The proposed device also offers three times better ESD robustness per unit area. Further the proposed SCR has no added capacitive loading and is compatible with standard process flow and design rules.

公开(公告)号：US20190013310A1

公开(公告)日：2019-01-10

申请号：US15883306

申请日：2018-01-30

Applicant: INDIAN INSTITUTE OF SCIENCE

Inventor： Milova PAUL ,  Mayank SHRIVASTAVA ,  B. Sampath KUMAR ,  Christian RUSS ,  Harald GOSSNER

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/78 ,  H01L29/06 ,  H01L29/20

Abstract: The present disclosure relates to a Dual Fin SCR device having two parallel fins on which cathode, anode, n- and p- type triggering taps are selectively doped, wherein one Fin (or group of parallel Fins) comprises anode and n-tap, and other Fin (or group of parallel Fins) comprises cathode and p-tap. As key regions of the proposed SCR (anode and cathode), which carry majority of current after triggering, are placed diagonally, they provide substantial benefit in terms of spreading current and dissipating heat. The proposed SCR ESD protection device helps obtain regenerative feedback between base—collector junctions of two back-to-back bipolar transistors, which enables the proposed SCR to shunt ESD current. The proposed SCR design enables lower trigger and holding voltage for efficient and robust ESD protection. The proposed SCR device/design helps offer a tunable trigger voltage and a holding voltage with highfailure threshold.

公开(公告)号：US20180226317A1

公开(公告)日：2018-08-09

申请号：US15883749

申请日：2018-01-30

Applicant: INDIAN INSTITUTE OF SCIENCE

Inventor： Mayank SHRIVASTAVA ,  Milova PAUL ,  Christian RUSS ,  Harald GOSSNER

IPC: H01L23/367 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/861 ,  H01L29/735 ,  H01L29/74

CPC classification number: H01L23/367 ,  H01L27/0248 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/735 ,  H01L29/7436 ,  H01L29/861 ,  H01L29/8613

Abstract: The present disclosure relates to a thermal management solution for ESD protection devices in advanced Fin- and/or Nanowire-based technology nodes, by employing localized nano heat sinks, which enable heat transport from local hot spots to surface of chip, which allows significant reduction in peak temperature for a given ESD current. In an aspect, the proposed semiconductor device can include at least one fin having a source and a drain disposed over a p-well or a n-well in a substrate; an electrically floating dummy metal gate disposed close to drain or hot spot over at least a portion of the at least one fin, and an electrical metal gate is disposed close to the source; and a nano-heat sink operatively coupled with the dummy metal gate and terminating at the surface of chip in which the semiconductor device is configured so as to enable transfer of heat received from the at least one fin through the dummy metal gate to the surface of the chip.