公开(公告)号：US20190067440A1

公开(公告)日：2019-02-28

申请号：US16114650

申请日：2018-08-28

Applicant: INDIAN INSTITUTE OF SCIENCE

Inventor： Mayank Shrivastava ,  Sayak Dutta Gupta ,  Ankit Soni ,  Srinivasan Raghavan ,  Navakanta Bhat

IPC: H01L29/49 ,  H01L29/778 ,  H01L21/02

Abstract: The present disclosure provides an improved enhancement mode field effect transistor (FET) having an oxide (AlxTi1-xO) emulating p-type gate. The present disclosure provides a novel enhancement mode High Electron Mobility Transistor (HEMT) structure with AlxTi1-xO Gate Oxide Engineering as Replacement of p-GaN Gate. In an aspect, the present disclosure provides a hybrid gate stack that combines p-GaN technology with the proposed oxide for e-mode operation. The HEMT structure with AlxTi1-xO Gate oxide provides a threshold voltage tuning from negative to positive by changing p-doping composition. Using a developed p-type oxide, e-mode device shows ON current ˜400 mA/mm, sub-threshold slope of 73 mV/dec, Ron=8.9 Ωmm, interface trap density

公开(公告)号：US11973137B2

公开(公告)日：2024-04-30

申请号：US17309583

申请日：2019-12-05

Applicant: Indian Institute of Science

Inventor： Srinivasan Raghavan ,  Navakanta Bhat ,  Rohith Soman

IPC: H01L29/778 ,  H01L29/06

CPC classification number: H01L29/7786 ,  H01L29/0638

Abstract: The present subject matter provides a High Mobility Electron Transistor (HEMT) comprising: a substrate, a nucleation layer provided on the substrate, a channel layer, and a buffer layer formed between the nucleation layer and the channel layer. The buffer layer comprises a vertical stack of p-n junctions. Each p-n junction of the vertical stack of p-n junctions comprises an n-type layer provided on a p-type layer. The n-type layer and the p-type layer are parallel to the substrate.

公开(公告)号：US10854719B2

公开(公告)日：2020-12-01

申请号：US15462294

申请日：2017-03-17

Applicant: INDIAN INSTITUTE OF SCIENCE

Inventor： Srinivasan Raghavan ,  Hareesh Chandrasekar ,  Nagaboopathy Mohan ,  Dhayalan Shakthivel

IPC: H01L29/20 ,  H01L21/02 ,  H01L21/768 ,  H01L29/04 ,  H01L29/16 ,  C30B25/18 ,  C30B25/04 ,  C30B29/40 ,  C30B29/60

Abstract: The present invention provides a metal nitride platform for semiconductor devices, including, a pre-defined array of catalyst sites, disposed on a substrate. Metal nitride islands with lateral to vertical size ratios of at least greater than one (1) are disposed on the array of catalyst sites, where the surfaces of the metal nitride islands are with reduced dislocation densities and side walls with bending of dislocations. The platform of metal nitride islands is further used to build electrically and optically-active devices. The present invention also provides a process for the preparation of a metal nitride platform, selectively, on the array of catalyst sites, in the presence of a reactive gas and precursors and under preferred reaction conditions, to grow metal nitride islands with lateral to vertical size ratios of at least greater than one (1).

公开(公告)号：US11522078B2

公开(公告)日：2022-12-06

申请号：US16629156

申请日：2018-07-06

Applicant: Indian Institute of Science

Inventor： Rohith Soman ,  Ankit Soni ,  Mayank Shrivastava ,  Srinivasan Raghavan ,  Navakant Bhat

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423

Abstract: A High Electron Mobility Transistor (HEMT) having a reduced surface field (RESURF) junction is provided. The HEMT includes a source electrode at a first end and a drain electrode at a second end. A gate electrode is provided between the source electrode and the drain electrode. A reduced surface field (RESURF) junction extends from the first end to the second end. The gate electrode is provided above the RESURF junction. A buried channel layer is formed in the RESURF junction on application of a positive voltage at the gate electrode. The RESURF junction includes an n-type Gallium nitride (GaN) layer and a p-type GaN layer. The n-type GaN layer is provided between the p-type GaN layer and the gate electrode.