公开(公告)号：US20040094830A1

公开(公告)日：2004-05-20

申请号：US10612744

申请日：2003-06-30

Applicant: Intel Corporation

Inventor： Quat T. Vu ,  Jian Li ,  Qing Ma ,  Maria V. Henao ,  Xiao-Chun Mu

IPC: H01L023/02

CPC classification number: H01L24/19 ,  H01L21/568 ,  H01L23/532 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  Y10T29/4935 ,  H01L2224/96 ,  H01L2224/82 ,  H01L2924/00

Abstract: A microelectronic package including a microelectronic die disposed within an opening in a microelectronic packaging core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic die. Build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulant material, and the microelectronic package core to form the microelectronic package.

公开(公告)号：US20020173133A1

公开(公告)日：2002-11-21

申请号：US09861689

申请日：2001-05-21

Applicant: Intel Corporation

Inventor： Steven Towle ,  Martha Jones ,  Quat T. Vu

IPC: H01L021/44

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Expanded bond pads are formed over a passivation layer on a semiconductor wafer before the wafer is diced into individual circuit chips. After dicing, the individual chips are packaged by fixing each chip within a package core and building up one or more metallization layers on the resulting assembly. In at least one embodiment, a high melting temperature (lead free) alternative bump metallurgy (ABM) form of controlled collapse chip connect (C4) processing is used to form relatively wide conducting platforms over the bond pads on the wafer.

Abstract translation: 在将晶片切割成单独的电路芯片之前，在半导体晶片上的钝化层上形成扩展焊盘。 在切割之后，通过将每个芯片固定在封装芯中并在所得组件上建立一个或多个金属化层来封装各个芯片。 在至少一个实施例中，使用可控崩溃芯片连接（C4）处理的高熔融温度（无铅）替代凸点冶金（ABM）形式在晶片上的接合焊盘上形成相对宽的导电平台。

公开(公告)号：US20020158334A1

公开(公告)日：2002-10-31

申请号：US09845881

申请日：2001-04-30

Applicant: Intel Corporation

Inventor： Quat T. Vu ,  Tuy T. Ton ,  Steven Towle

IPC: H01L023/02

CPC classification number: H01L23/16 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/2413 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/00

Abstract: A microelectronic device includes a microelectronic die having an interfacial metal layer deposited over an active surface thereof to perform a signal distribution function within the device. The microelectronic die is fixed within a package core to form a die/core assembly. One or more metallization layers may then be built up over the die/core assembly as part of a packaging scheme. The interfacial metal layer can be applied either before or after the die is fixed within the package core. In one approach, the interfacial layer is applied during wafer-level processing.

Abstract translation: 微电子器件包括具有沉积在其有效表面上的界面金属层的微电子管芯，以在器件内执行信号分配功能。 微电子管芯固定在封装芯内以形成芯/芯组件。 然后可以将一个或多个金属化层作为包装方案的一部分在模具/芯组件上形成。 界面金属层可以在芯片固定在封装芯内之前或之后施加。 在一种方法中，在晶片级处理期间施加界面层。