公开(公告)号：US20240413550A1

公开(公告)日：2024-12-12

申请号：US18805632

申请日：2024-08-15

Applicant: Intel Corporation

Inventor： Chenghai Yan ,  Wenzhi Wang ,  Qihang Shang ,  Tao Xu ,  Weijiao Jiang ,  Xinjun Zhang ,  Lei Wang ,  Xiaorui Xu

IPC: H01R12/70 ,  H01R13/6461

Abstract: An apparatus and method for reducing differential cross-talk in a CPU pin arrangement of a server motherboard are described. The CPU pin arrangement has pin patterns that are arranged in a square, separated from each other, and are mirrored around an axis between the pin patterns. Each pin pattern has pins that each include a main body with a lateral asymmetric cross-section, a first connector extending from one end of the main body and coupled to the motherboard through solder, and a second connector extending from an opposing end of the main body and coupled to the CPU through a pressure contact.

公开(公告)号：US20240274521A1

公开(公告)日：2024-08-15

申请号：US18570455

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Chenghai Yan ,  Lei Wang ,  Maoxin Yin ,  Wenzhi Wang

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/66

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/66 ,  H01L24/14 ,  H01L24/16 ,  H01L2223/6661 ,  H01L2224/1403 ,  H01L2224/16227

Abstract: Methods, apparatus, systems, and articles of manufacture to reduce impedance discontinuities and crosstalk in integrated circuit packages are disclosed. A disclosed apparatus includes: a package substrate, and a ball grid array on a first surface of the package substrate. The ball grid array includes a first ball and a second ball adjacent the first ball. The ball grid array is to enable the package substrate to be electrically coupled to a circuit board. The apparatus further includes a metal interconnect within the package substrate. The metal interconnect is electrically coupled to the first ball. The metal interconnect includes an inductive loop that extends toward the second ball.

公开(公告)号：US20240088069A1

公开(公告)日：2024-03-14

申请号：US18260810

申请日：2021-02-26

Applicant: Intel Corporation

Inventor： Wenzhi Wang ,  Xiaoning Ye ,  Yunhui Chu ,  Chunfei Ye ,  James A. McCall

IPC: H01L23/66 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/66 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5386 ,  H01L25/18 ,  H10B80/00 ,  H01L2223/6627

Abstract: Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a plurality of microstrips and a plurality of conductive segments. Individual ones of the conductive segments may be at least partially over at least two microstrips, a dielectric material may be between the plurality of microstrips and the plurality of conductive segments, and the conductive segments are included in a tape.

公开(公告)号：US20240063134A1

公开(公告)日：2024-02-22

申请号：US18260805

申请日：2021-02-26

Applicant: Intel Corporation

Inventor： Xiaoning Ye ,  Pooya Tadayon ,  Wenzhi Wang ,  Srinivasa R. Aravamudhan ,  Nathan Somnang Tan ,  Brett Daniel Grossman

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L25/0655 ,  H01L23/5383 ,  H01L23/49894 ,  H01L23/49877 ,  H01L2224/16225 ,  H01L24/16

Abstract: Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a plurality of microstrips and a plurality of conductive segments. Individual ones of the conductive segments may be at least partially over at least two microstrips, a dielectric material may be between the plurality of microstrips and the plurality of conductive segments, and an individual conductive segment may have a conductivity that is close to or less than a conductivity of a conductive line of an individual microstrip.