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公开(公告)号：US20150353353A1
公开(公告)日：2015-12-10
申请号：US14827214
申请日：2015-08-14
Applicant: Invensense, Inc.
Inventor： Cerina Zhang , Nim Tea
IPC: B81C1/00
CPC classification number: B81C1/00984 , B81B3/0008 , B81B2207/015 , B81C1/00976 , B81C2201/115 , H01L21/76838 , H01L23/48 , H01L2924/0002 , H01L2924/00
Abstract: A method of the invention includes reducing stiction of a MEMS device by providing a conductive path for electric charge collected on a bump stop formed on a substrate. The bump stop is formed by depositing and patterning a dielectric material on the substrate, and the conductive path is provided by a conductive layer deposited on the bump stop. The conductive layer can also be roughened to reduce stiction.
Abstract translation: 本发明的一种方法包括通过为形成在衬底上的凸点块上收集的电荷提供导电路径来减少MEMS器件的静电。 通过在衬底上沉积和图案化介电材料形成凹凸块，并且通过沉积在凸块上的导电层提供导电路径。 导电层也可以被粗糙化以减少粘性。
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公开(公告)号：US09731963B2
公开(公告)日：2017-08-15
申请号：US15265668
申请日：2016-09-14
Applicant: InvenSense, Inc.
Inventor： Cerina Zhang , Martin Lim , Jongwoo Shin , Joseph Seeger
CPC classification number: B81C1/00301 , B81B7/007 , B81B7/02 , B81B2201/0235 , B81B2201/0242 , B81C1/0023 , B81C1/00238 , B81C1/00246 , B81C1/00269 , B81C2201/0104 , B81C2201/0132 , B81C2203/0145 , B81C2203/019 , B81C2203/035 , B81C2203/0792
Abstract: Semiconductor manufacturing processes include providing a first substrate having a first passivation layer disposed above a patterned top-level metal layer, and further having a second passivation layer disposed over the first passivation layer; the second passivation layer has a top surface. The processes further include forming an opening in a first portion of the second passivation layer, and the opening exposes a portion of a surface of the first passivation layer. The processes further include patterning the second and first passivation layers to expose portions of the patterned top-level metal layer and bonding a second substrate and the first substrate to each other. The bonding occurs within a temperature range in which at least the exposed portion of the first passivation layer undergoes outgassing.
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公开(公告)号：US09650241B2
公开(公告)日：2017-05-16
申请号：US14857687
申请日：2015-09-17
Applicant: InvenSense, Inc.
Inventor： Cerina Zhang , Martin Lim
CPC classification number: B81C1/00333 , B81B3/0051 , B81B7/02 , B81B2201/0235 , B81B2201/0242 , B81B2203/0315 , B81B2207/012 , B81B2207/07 , B81C2203/0118 , B81C2203/0145 , B81C2203/035 , B81C2203/038
Abstract: A method for forming a MEMS device includes coupling a MEMS substrate and a base substrate. The MEMS substrate and the base substrate contain at least two enclosures. One enclosures has a first vertical gap between the bonding surface of the MEMS substrate and the bonding surface of the base substrate that is less than a second vertical gap between the bonding surface of the MEMS substrate and the bonding surface of the base substrate than another of the enclosures to provide a height difference between the first vertical gap and the second vertical gap. The method includes bonding the bonding surfaces of the one of the two enclosures at a first pressure to provide a first sealed enclosure. The method includes bonding the bonding surfaces of other of the two enclosures at a second pressure to provide a second sealed enclosure.
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4.发明授权公开(公告)号：US09452925B2
公开(公告)日：2016-09-27
申请号：US14832786
申请日：2015-08-21
Applicant: InvenSense, Inc.
Inventor： Cerina Zhang , Martin Lim , Jongwoo Shin , Joseph Seeger
CPC classification number: B81C1/00301 , B81B7/007 , B81B7/02 , B81B2201/0235 , B81B2201/0242 , B81C1/0023 , B81C1/00238 , B81C1/00246 , B81C1/00269 , B81C2201/0104 , B81C2201/0132 , B81C2203/0145 , B81C2203/019 , B81C2203/035 , B81C2203/0792
Abstract: Semiconductor manufacturing processes include providing a first substrate having a first passivation layer disposed above a patterned top-level metal layer, and further having a second passivation layer disposed over the first passivation layer; the second passivation layer has a top surface. The processes further include forming an opening in a first portion of the second passivation layer, and the opening exposes a portion of a surface of the first passivation layer. The processes further include patterning the second and first passivation layers to expose portions of the patterned top-level metal layer and bonding a second substrate and the first substrate to each other. The bonding occurs within a temperature range in which at least the exposed portion of the first passivation layer undergoes outgassing.
Abstract translation: 半导体制造工艺包括提供第一衬底，其具有设置在图案化顶层金属层上方的第一钝化层，并且还具有设置在第一钝化层上的第二钝化层; 第二钝化层具有顶表面。 所述方法还包括在第二钝化层的第一部分中形成开口，并且开口暴露第一钝化层的表面的一部分。 所述方法还包括图案化第二钝化层和第一钝化层以暴露图案化顶层金属层的部分并将第二衬底和第一衬底彼此结合。 接合发生在至少第一钝化层的暴露部分经历脱气的温度范围内。
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Patent Agency Ranking
公开(公告)号：US09926192B2
公开(公告)日：2018-03-27
申请号：US14827214
申请日：2015-08-14
Applicant: Invensense, Inc.
Inventor： Cerina Zhang , Nim Tea
IPC: H01L21/44 , B81C1/00 , H01L21/768 , H01L23/48 , B81B3/00
CPC classification number: B81C1/00984 , B81B3/0008 , B81B2207/015 , B81C1/00976 , B81C2201/115 , H01L21/76838 , H01L23/48 , H01L2924/0002 , H01L2924/00
Abstract: A method of the invention includes reducing stiction of a MEMS device by providing a conductive path for electric charge collected on a bump stop formed on a substrate. The bump stop is formed by depositing and patterning a dielectric material on the substrate, and the conductive path is provided by a conductive layer deposited on the bump stop. The conductive layer can also be roughened to reduce stiction.
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公开(公告)号：US20140353774A1
公开(公告)日：2014-12-04
申请号：US13909842
申请日：2013-06-04
Applicant: Invensense, Inc.
Inventor： Cerina Zhang , Nim Tea
IPC: H01L21/768 , H01L23/48 , H01L29/84
CPC classification number: B81C1/00984 , B81B3/0008 , B81B2207/015 , B81C1/00976 , B81C2201/115 , H01L21/76838 , H01L23/48 , H01L2924/0002 , H01L2924/00
Abstract: A method of the invention includes reducing stiction of a MEMS device by providing a conductive path for electric charge collected on a bump stop formed on a substrate. The bump stop is formed by depositing and patterning a dielectric material on the substrate, and the conductive path is provided by a conductive layer deposited on the bump stop. The conductive layer can also be roughened to reduce stiction.
Abstract translation: 本发明的一种方法包括通过为形成在衬底上的凸点块上收集的电荷提供导电路径来减少MEMS器件的静电。 通过在衬底上沉积和图案化介电材料形成凹凸块，并且通过沉积在凸块上的导电层提供导电路径。 导电层也可以被粗糙化以减少粘性。
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公开(公告)号：US09738511B2
公开(公告)日：2017-08-22
申请号：US14225275
申请日：2014-03-25
Applicant: InvenSense, Inc.
Inventor： Jongwoo Shin , Kirt Reed Williams , Cerina Zhang , Kuolung (Dino) Lei
CPC classification number: B81C1/00103 , B81C2201/0112 , B81C2201/0132 , B81C2201/0133
Abstract: A MEMS (microelectromechanical systems) structure comprises a MEMS wafer. A MEMS wafer includes a cap with cavities bonded to a structural layer through a dielectric layer disposed between the cap and the structural layer. Unique configurations of MEMS devices and methods of providing such are set forth which provide for, in part, creating rounded, scalloped or chamfered MEMS profiles by shaping the etch mask photoresist reflow, by using a multi-step deep reactive ion etch (DRIE) with different etch characteristics, or by etching after DRIE.
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8.发明申请公开(公告)号：US20150360939A1
公开(公告)日：2015-12-17
申请号：US14832786
申请日：2015-08-21
Applicant: InvenSense, Inc.
Inventor： Cerina Zhang , Martin Lim , Jongwoo Shin , Joseph Seeger
IPC: B81C1/00
CPC classification number: B81C1/00301 , B81B7/007 , B81B7/02 , B81B2201/0235 , B81B2201/0242 , B81C1/0023 , B81C1/00238 , B81C1/00246 , B81C1/00269 , B81C2201/0104 , B81C2201/0132 , B81C2203/0145 , B81C2203/019 , B81C2203/035 , B81C2203/0792
Abstract: Semiconductor manufacturing processes include providing a first substrate having a first passivation layer disposed above a patterned top-level metal layer, and further having a second passivation layer disposed over the first passivation layer; the second passivation layer has a top surface. The processes further include forming an opening in a first portion of the second passivation layer, and the opening exposes a portion of a surface of the first passivation layer. The processes further include patterning the second and first passivation layers to expose portions of the patterned top-level metal layer and bonding a second substrate and the first substrate to each other. The bonding occurs within a temperature range in which at least the exposed portion of the first passivation layer undergoes outgassing.
Abstract translation: 半导体制造工艺包括提供第一衬底，其具有设置在图案化顶层金属层上方的第一钝化层，并且还具有设置在第一钝化层上的第二钝化层; 第二钝化层具有顶表面。 所述方法还包括在第二钝化层的第一部分中形成开口，并且开口暴露第一钝化层的表面的一部分。 所述方法还包括图案化第二钝化层和第一钝化层以暴露图案化顶层金属层的部分并将第二基板和第一基板彼此接合。 接合发生在至少第一钝化层的暴露部分经历脱气的温度范围内。
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公开(公告)号：US09136165B2
公开(公告)日：2015-09-15
申请号：US13909842
申请日：2013-06-04
Applicant: Invensense, Inc.
Inventor： Cerina Zhang , Nim Tea
IPC: H01L21/768 , H01L23/48
CPC classification number: B81C1/00984 , B81B3/0008 , B81B2207/015 , B81C1/00976 , B81C2201/115 , H01L21/76838 , H01L23/48 , H01L2924/0002 , H01L2924/00
Abstract: A method of the invention includes reducing stiction of a MEMS device by providing a conductive path for electric charge collected on a bump stop formed on a substrate. The bump stop is formed by depositing and patterning a dielectric material on the substrate, and the conductive path is provided by a conductive layer deposited on the bump stop. The conductive layer can also be roughened to reduce stiction.
Abstract translation: 本发明的一种方法包括通过为形成在衬底上的凸点块上收集的电荷提供导电路径来减少MEMS器件的静电。 通过在衬底上沉积和图案化介电材料形成凹凸块，并且通过沉积在凸块上的导电层提供导电路径。 导电层也可以被粗糙化以减少粘性。
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