公开(公告)号：US20240057249A1

公开(公告)日：2024-02-15

申请号：US18446487

申请日：2023-08-09

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  HeeSoo LEE ,  YeJin PARK

IPC: H05K1/02 ,  H05K1/18 ,  H01L25/16 ,  H01L23/31 ,  H01L23/552 ,  H05K9/00 ,  H01L21/56 ,  H05K3/28

CPC classification number: H05K1/0271 ,  H05K1/18 ,  H01L25/16 ,  H01L23/3121 ,  H01L23/552 ,  H05K9/0022 ,  H01L21/56 ,  H05K3/284 ,  H05K2201/2009 ,  H05K2201/10189 ,  H05K2203/1316 ,  H05K2203/1322

Abstract: An electronic package comprises: a substrate comprising a first region and a second region adjacent to the first region in a lengthwise direction of the substrate; a first electronic component mounted on the substrate in the first region; a second electronic component mounted on the substrate in the second region, wherein the second electronic component does not occupy an entirety of the substrate in a widthwise direction of the substrate; and an encapsulant layer formed on the substrate, wherein at least the second electronic component is exposed from the encapsulant layer, and wherein the encapsulant layer extends from the first region to the second region to reinforce the substrate in both the first region and the second region.

公开(公告)号：US20240120289A1

公开(公告)日：2024-04-11

申请号：US18475249

申请日：2023-09-27

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  YeJin PARK ,  HeeSoo LEE

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/498 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0655 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/6677 ,  H01L2224/16155 ,  H01L2224/16225 ,  H01L2224/32146 ,  H01L2224/32225 ,  H01L2924/142 ,  H01L2924/1431 ,  H01L2924/182 ,  H01L2924/3025

Abstract: An electronic package is provided. The electronic package comprises a substrate having a first region and a second region; a first set of electronic components mounted on the substrate in the first region; a second set of electronic components mounted on the substrate in the second region; an encapsulant layer disposed on the substrate and encapsulating the first and second sets of electronic components; a set of interconnect components disposed on the substrate in the second region, and extending through the encapsulant layer, wherein the set of interconnect components are electrically coupled to the first and second sets of electronic components; and a connector mounted on the encapsulant layer and electrically coupled to the first and second sets of electronic components through the set of interconnect components.

公开(公告)号：US20240421015A1

公开(公告)日：2024-12-19

申请号：US18746135

申请日：2024-06-18

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  YeJin PARK ,  HeeSoo LEE ,  HyunSu TAK ,  SangJun PARK

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/14 ,  H01L23/552 ,  H01L25/16 ,  H01R12/52

Abstract: A semiconductor package is disclosed. The semiconductor package comprises: a metal shim, a package substrate attached onto a front side of the metal shim, wherein the package substrate comprises an opening that passes therethrough; one or more electronic components mounted on the package substrate; an encapsulant layer partially formed on the package substrate to expose a region of the package substrate and the opening of the package substrate, wherein the encapsulant layer encapsulates the one or more electronic components on the package substrate; a first connector mounted in the exposed region of the package substrate; a second connector mounted in the encapsulant layer and on the package substrate; and a magnet mounted in the opening of the package substrate and extending from the metal shim through the package substrate and the encapsulant layer.

公开(公告)号：US20240055367A1

公开(公告)日：2024-02-15

申请号：US18363773

申请日：2023-08-02

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： EunByeol LEE ,  DooSoub SHIN ,  YeJin PARK ,  HyukCheon KWON

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L23/3128 ,  H01Q1/2283

Abstract: Provided is a method for forming a partial shielding for an electronic assembly, comprising: providing an electronic assembly mounted on a mother board, wherein the electronic assembly comprises a substrate, and at least one electronic component and a conductive pattern mounted on a top surface of the substrate; disposing a mask onto the substrate to cover the at least one electronic component; forming an encapsulant layer on the mother board to encapsulate at least the electronic assembly; forming a trench through the encapsulant layer to expose at least a portion of the conductive pattern and at least a portion of lateral surfaces of the mask; forming a shielding layer on the mother board to cover the encapsulant layer and fill in the trench; and detaching the mask from the mother board.