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    Floating gate memory array device with improved program and read performance
    1.
    发明授权
    Floating gate memory array device with improved program and read performance 失效
    浮栅存储器阵列器件具有改进的程序和读取性能

    公开(公告)号：US5862073A

    公开(公告)日：1999-01-19

    申请号：US931065

    申请日：1997-09-15

    Applicant: Jun-Lin Yeh ,  Ya-Chun Chang

    Inventor： Jun-Lin Yeh ,  Ya-Chun Chang

    IPC: G11C16/04 ,  G11C16/08 ,  G11C7/00

    CPC classification number: G11C16/08 ,  G11C16/0416

    Abstract: A semiconductor memory array and method for use in a memory device in which the location of a memory cell in the array is specified by row address and column address decoders. The memory cells may be floating gate memory cells in which data is programmed by hot carrier injection and erased by Fowler-Nordheim tunneling. The array includes bit lines connected to the column address decoder, and word lines and N+ diffusion source lines connected to the row address decoder. Each memory cell has a gate connected to a word line, a drain connected to a bit line and a source connected to the N+ diffusion source line. A low resistance source line formed of metal II or other conductive material is arranged adjacent to each N+ source line and is electrically connected thereto at one or more locations via interconnecting straps. The low resistance source lines serve to reduce the voltage drop across the N+ diffusion source lines during program operations and provide an improved ground connection during read operations. The word lines are grouped into pairs of even and odd word lines and each pair makes up the minimum program unit or page. The page is also the minimum erase unit, such that adjacent even and odd word lines are erased simultaneously. The voltage applied to a given word line during a read operation may be supplied by a word line clamping circuit which limits gate disturbances resulting from fluctuations in supply voltage.

    Abstract translation: 一种在存储器件中使用的半导体存储器阵列和方法，其中阵列中的存储单元的位置由行地址和列地址解码器指定。 存储器单元可以是浮动栅极存储单元，其中通过热载流子注入来编程数据，并通过Fowler-Nordheim隧道擦除数据。 阵列包括连接到列地址解码器的位线，以及连接到行地址解码器的字线和N +扩散源线。 每个存储单元具有连接到字线的栅极，连接到位线的漏极和连接到N +扩散源线的源极。 由金属II或其他导电材料形成的低电阻源极线布置成与每个N +源极线相邻，并且通过互连带在一个或多个位置处电连接到其上。 低电阻源线用于在编程操作期间减小N +扩散源线上的电压降，并在读取操作期间提供改进的接地连接。 字线被分组成偶数和奇数字线对，每对组成最小程序单元或页面。 该页面也是最小擦除单元，使得相邻的偶数和奇数字线同时被擦除。 在读取操作期间施加到给定字线的电压可以由限制由电源电压波动引起的栅极干扰的字线钳位电路提供。

    FLASH MEMORY AND FLASH MEMORY ACCESSING METHOD
    2.
    发明申请
    FLASH MEMORY AND FLASH MEMORY ACCESSING METHOD 审中-公开
    闪存存储器和闪速存储器访问方法

    公开(公告)号：US20120246384A1

    公开(公告)日：2012-09-27

    申请号：US13053194

    申请日：2011-03-21

    Applicant: Chi-Cheng Lin ,  Jun-Lin Yeh

    Inventor： Chi-Cheng Lin ,  Jun-Lin Yeh

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F11/0757 ,  G06F11/1417

    Abstract: A flash memory accessing method is provided. The method includes: firstly, dividing the flash memory into a primary storage area and a backup storage area, wherein the difference between a first start address of the primary storage area and a second start address of the backup storage area is an offset address not equal to zero; reading the flash memory according to a address pointer equal to the first start address so as to obtain the boot data; making the electronic apparatus perform a boot sequence according to the boot data; then, detecting whether the boot sequence is normal or not, and when the boot sequence is abnormal, providing the flash memory with changing the read pointer to the second start address according to an offset address to read the backup boot data.

    Abstract translation: 提供闪速存取存取方法。 该方法包括：首先将闪存分为主存储区和备份存储区，其中主存储区的第一起始地址与备份存储区的第二起始地址之间的差是偏移地址不等于 到零 根据等于第一起始地址的地址指针读取闪存，以获得引导数据; 使电子装置根据引导数据执行引导顺序; 然后，检测引导顺序是否正常，并且当引导顺序异常时，根据偏移地址提供将读指针改变到第二起始地址的闪存，以读取备份引导数据。

    Multi-zone temperature control for semiconductor wafer
    4.
    发明授权
    Multi-zone temperature control for semiconductor wafer 有权
    半导体晶圆的多区域温度控制

    公开(公告)号：US08404572B2

    公开(公告)日：2013-03-26

    申请号：US12370746

    申请日：2009-02-13

    Applicant: Chun-Lin Chang ,  Hsin-Hsien Wu ,  Zin-Chang Wei ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Jun-Lin Yeh ,  Jih-Jse Lin ,  Jo-Fei Wang ,  Ming-Yu Fan ,  Jong-I Mou

    Inventor： Chun-Lin Chang ,  Hsin-Hsien Wu ,  Zin-Chang Wei ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Jun-Lin Yeh ,  Jih-Jse Lin ,  Jo-Fei Wang ,  Ming-Yu Fan ,  Jong-I Mou

    IPC: H01L21/425

    CPC classification number: H01L22/20 ,  H01L21/67248 ,  H01L21/67253 ,  H01L22/12

    Abstract: An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.

    Abstract translation: 一种装置包括被配置为执行离子注入工艺的处理室。 在处理室内设有冷却台板或静电吸盘。 冷却台板或静电卡盘构造成支撑半导体晶片。 冷却台板或静电卡盘具有多个温度区域。 每个温度区域包括在冷却压板或静电卡盘内或附近的至少一个流体导管。 提供至少两个冷却剂源，每个冷却剂源流体耦合到相应的一个流体导管，并且构造成在离子注入过程期间将分别不同的冷却剂供应到多个温度区中的相应的一个温度区。 冷却剂源分别包括不同的冷却或制冷装置。

    FLASH MEMORY APPARATUS WITH SERIAL INTERFACE AND RESET METHOD THEREOF
    5.
    发明申请
    FLASH MEMORY APPARATUS WITH SERIAL INTERFACE AND RESET METHOD THEREOF 有权
    具有串行接口的闪存设备及其复位方法

    公开(公告)号：US20120221766A1

    公开(公告)日：2012-08-30

    申请号：US13034683

    申请日：2011-02-24

    Applicant: Jun-Lin Yeh ,  Chi-Cheng Lin

    Inventor： Jun-Lin Yeh ,  Chi-Cheng Lin

    IPC: G06F12/00

    CPC classification number: G06F9/30043 ,  G06F12/00 ,  G06F12/0246 ,  G06F2212/7206 ,  G11C16/20 ,  G11C16/22 ,  G11C2216/30

    Abstract: A flash memory apparatus with serial interface is disclosed. The flash memory apparatus includes a selector, a core circuit and a programmable data bank. The selector decides whether or not to connect one of a write protect pin and a hold pin to a reset signal line. The core circuit receives a reset signal transmitted by the reset signal line and activates a reset operation accordingly. A selecting data is written into the programmable data bank through a programming method and the programmable data bank outputs the selecting data to serve as a selecting signal.

    Abstract translation: 公开了具有串行接口的闪存装置。 闪存装置包括选择器，核心电路和可编程数据组。 选择器决定是否将写保护引脚和保持引脚之一连接到复位信号线。 核心电路接收由复位信号线发送的复位信号，并相应地启动复位操作。 通过编程方法将选择数据写入可编程数据库，并且可编程数据组输出选择数据以用作选择信号。

    Device and method for compensating defect in semiconductor memory
    6.
    发明授权
    Device and method for compensating defect in semiconductor memory 有权
    半导体存储器补偿缺陷的装置和方法

    公开(公告)号：US07203107B2

    公开(公告)日：2007-04-10

    申请号：US11306381

    申请日：2005-12-27

    Applicant: Jun-Lin Yeh

    Inventor： Jun-Lin Yeh

    IPC: G11C29/00 ,  G11C7/00

    CPC classification number: G11C29/883 ,  G11C29/88

    Abstract: A device for compensating a semiconductor memory defect, suitable for use in a semiconductor memory, is provided. The device includes a memory array, having at least a defectless sub-memory region, the memory array being coupled to an address decoder circuit and a sensing circuit for storing data. A selection circuit is coupled to a control unit and outputs a selection signal to the control unit. A first input address buffer is coupled to the control unit and the address decoder circuit, and outputs an address signal to the address decoder circuit in response to the selection signal for selecting the defectless sub-memory region to store data. A method for compensating a semiconductor memory defect is also provided, including determining whether the memory region of the semiconductor memory has a defect; and replacing the memory region with the defectless sub-memory region to store data when the semiconductor memory is defective.

    Abstract translation: 提供一种适用于半导体存储器的用于补偿半导体存储器缺陷的装置。 该装置包括具有至少一个无缺陷的子存储器区域的存储器阵列，该存储器阵列耦合到地址解码器电路和用于存储数据的感测电路。 选择电路耦合到控制单元并将选择信号输出到控制单元。 第一输入地址缓冲器耦合到控制单元和地址解码器电路，并且响应于用于选择无缺陷子存储器区域以存储数据的选择信号而将地址信号输出到地址解码器电路。 还提供了一种用于补偿半导体存储器缺陷的方法，包括确定半导体存储器的存储区是否具有缺陷; 以及当半导体存储器有缺陷时用无缺陷子存储器区域替换存储区域以存储数据。

    Flash memory apparatus with serial interface and reset method thereof
    7.
    发明授权
    Flash memory apparatus with serial interface and reset method thereof 有权
    具有串行接口的闪存装置及其复位方法

    公开(公告)号：US08914569B2

    公开(公告)日：2014-12-16

    申请号：US13034683

    申请日：2011-02-24

    Applicant: Jun-Lin Yeh ,  Chi-Cheng Lin

    Inventor： Jun-Lin Yeh ,  Chi-Cheng Lin

    IPC: G06F12/00 ,  G06F12/02 ,  G11C16/20 ,  G11C16/22

    CPC classification number: G06F9/30043 ,  G06F12/00 ,  G06F12/0246 ,  G06F2212/7206 ,  G11C16/20 ,  G11C16/22 ,  G11C2216/30

    Abstract: A flash memory apparatus with serial interface is disclosed. The flash memory apparatus includes a selector, a core circuit and a programmable data bank. The selector decides whether or not to connect one of a write protect pin and a hold pin to a reset signal line. The core circuit receives a reset signal transmitted by the reset signal line and activates a reset operation accordingly. A selecting data is written into the programmable data bank through a programming method and the programmable data bank outputs the selecting data to serve as a selecting signal.

    Abstract translation: 公开了具有串行接口的闪存装置。 闪存装置包括选择器，核心电路和可编程数据组。 选择器决定是否将写保护引脚和保持引脚之一连接到复位信号线。 核心电路接收由复位信号线发送的复位信号，并相应地启动复位操作。 通过编程方法将选择数据写入可编程数据库，并且可编程数据组输出选择数据以用作选择信号。

    DEVICE AND METHOD FOR COMPENSATING DEFECT IN SEMICONDUCTOR MEMORY
    10.
    发明申请
    DEVICE AND METHOD FOR COMPENSATING DEFECT IN SEMICONDUCTOR MEMORY 有权
    用于补偿半导体存储器中的缺陷的装置和方法

    公开(公告)号：US20060203579A1

    公开(公告)日：2006-09-14

    申请号：US11306381

    申请日：2005-12-27

    Applicant: Jun-Lin Yeh

    Inventor： Jun-Lin Yeh

    IPC: G11C29/00 ,  G11C7/00

    CPC classification number: G11C29/883 ,  G11C29/88

    Abstract: A device for compensating a semiconductor memory defect, suitable for use in a semiconductor memory, is provided. The device includes a memory array, having at least a defectless sub-memory region, the memory array being coupled to an address decoder circuit and a sensing circuit for storing data. A selection circuit is coupled to a control unit and outputs a selection signal to the control unit. A first input address buffer is coupled to the control unit and the address decoder circuit, and outputs an address signal to the address decoder circuit in response to the selection signal for selecting the defectless sub-memory region to store data. A method for compensating a semiconductor memory defect is also provided, including determining whether the memory region of the semiconductor memory has a defect; and replacing the memory region with the defectless sub-memory region to store data when the semiconductor memory is defective.

    Abstract translation: 提供一种适用于半导体存储器的用于补偿半导体存储器缺陷的装置。 该装置包括具有至少一个无缺陷的子存储器区域的存储器阵列，该存储器阵列耦合到地址解码器电路和用于存储数据的感测电路。 选择电路耦合到控制单元并将选择信号输出到控制单元。 第一输入地址缓冲器耦合到控制单元和地址解码器电路，并且响应于用于选择无缺陷子存储器区域以存储数据的选择信号而将地址信号输出到地址解码器电路。 还提供了一种用于补偿半导体存储器缺陷的方法，包括确定半导体存储器的存储区是否具有缺陷; 以及当半导体存储器有缺陷时用无缺陷子存储器区域替换存储区域以存储数据。

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