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    Method for enhancing electrode surface area in DRAM cell capacitors
    3.
    发明申请
    Method for enhancing electrode surface area in DRAM cell capacitors 失效

    公开(公告)号：US20030203508A1

    公开(公告)日：2003-10-30

    申请号：US10408358

    申请日：2003-04-07

    Applicant: Micron Technology, Inc.

    Inventor： Donald L. Yates ,  Garry A. Mercaldi ,  James J. Hofmann

    IPC: H01L021/00

    CPC classification number: H01L27/1085 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/82 ,  H01L28/84 ,  H01L28/91

    Abstract: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface. In another embodiment of a method of forming the lower electrode, the texturizing underlayer is formed by depositing overlying first and second conductive metal layers and annealing the metal layers to form surface dislocations, preferably structured as a periodic network. A conductive metal is then deposited in gaseous phase, and agglomerates onto the surface dislocations of the texturizing layer, forming nanostructures in the form of island clusters. The capacitor is completed by depositing a dielectric layer over the formed lower electrode, and forming an upper capacitor electrode over the dielectric layer. The capacitors are particularly useful in fabricating DRAM cells.

    Method and composite for decreasing charge leakage
    6.
    发明申请
    Method and composite for decreasing charge leakage 失效
    减少电荷泄漏的方法和复合材料

    公开(公告)号：US20020093063A1

    公开(公告)日：2002-07-18

    申请号：US10060451

    申请日：2002-01-30

    Applicant: Micron Technology, Inc.

    Inventor： Michael Nuttall ,  Garry A. Mercaldi

    IPC: H01L029/76

    CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/511 ,  Y10S438/954

    Abstract: A dielectric insulating composite for insulating a floating gate from a control gate in a non-volatile memory is described. A material, such as an undoped polysilicon, amorphous silicon, or amorphous polysilicon or a silicon rich nitride, is inserted in the gate structure. The oxide film that results from the oxidation of these films is relatively free from impurities. As a result, charge leakage between the floating gate and control gate is reduced.

    Abstract translation: 描述了用于将浮动栅极与非易失性存储器中的控制栅极绝缘的绝缘绝缘复合材料。 诸如未掺杂的多晶硅，非晶硅或无定形多晶硅或富含硅的氮化物的材料插入栅极结构中。 由这些膜的氧化产生的氧化膜相对不含杂质。 结果，浮栅和控制栅之间的电荷泄漏减小。

    Localized masking for semiconductor structure development
    8.
    发明申请
    Localized masking for semiconductor structure development 有权
    半导体结构开发的局部掩蔽

    公开(公告)号：US20020024086A1

    公开(公告)日：2002-02-28

    申请号：US09912151

    申请日：2001-07-24

    Applicant: Micron Technology, Inc.

    Inventor： Donald L. Yates ,  Garry A. Mercaldi

    IPC: H01L027/108 ,  H01L021/8242 ,  H01L021/20

    CPC classification number: H01L28/92 ,  G03F7/0035 ,  G03F7/201 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0275 ,  H01L21/32139 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91

    Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

    Abstract translation: 用于集成电路的容器结构及其制造方法，而不使用机械平面化（例如化学机械平面化（CMP）），从而消除了CMP引起的缺陷和变化。 该方法利用在非机械去除暴露的表面层期间的孔的局部掩蔽来保护孔的内部。 通过将抗蚀剂层与电磁或热能的差分曝光来实现局部掩蔽。 容器结构适用于并入这种存储单元的存储器单元和装置以及其它集成电路。

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