公开(公告)号：US20250103076A1

公开(公告)日：2025-03-27

申请号：US18894507

申请日：2024-09-24

Applicant: NVIDIA Corp.

Inventor： Siddharth Saxena ,  Sudhir Shrikantha Kudva ,  Miguel Rodriguez ,  Vijay Srinivasan ,  Tezaswi Raja ,  Tom Gray ,  Santosh Santosh

IPC: G05F1/56 ,  G04F10/00 ,  H03M7/16

Abstract: Reference voltage generators including a header circuit configured to pass current from a power supply to a time-to-digital converter, an amount of the current to pass determined by a thermometer code, and logic to update the thermometer code based on a comparison between an output of the time-to-digital converter and a digital code representing a reference voltage level.

公开(公告)号：US20250105734A1

公开(公告)日：2025-03-27

申请号：US18895180

申请日：2024-09-24

Applicant: NVIDIA Corp.

Inventor： Siddharth Saxena ,  Sudhir Shrikantha Kudva ,  Miguel Rodriguez ,  Vijay Srinivasan ,  Tezaswi Raja ,  Carl Thomas Gray ,  Santosh Santosh

IPC: H02M3/155 ,  H01L23/528

Abstract: Power delivery systems for integrated circuits that include a first metal path traversing first metal layers from a global power domain supply to a voltage regulator, a second metal path traversing second metal layers from a local power domain supply to the voltage regulator, and a third metal path traversing third metal layers from the local power domain supply to an integrated circuit. Electrical isolation gaps are formed between the first metal layers, the second metal layers, and the third metal layers.