公开(公告)号：US09237005B2

公开(公告)日：2016-01-12

申请号：US14641454

申请日：2015-03-09

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Ming Chen ,  An-Chung Chen

IPC: H04L7/04 ,  H04L7/033 ,  H03L7/085 ,  H04L7/00

CPC classification number: H04L7/04 ,  H03L7/085 ,  H04L7/0054 ,  H04L7/033 ,  H04L7/0331

Abstract: A clock data recovery circuit module including a clock recovery circuit, a frequency comparison circuit and a signal detecting circuit is provided. The clock recovery circuit is configured to output a data recovery stream and a data recovery clock based on an input signal and a clock signal. The frequency comparison circuit is coupled to the clock recovery circuit. The frequency comparison circuit is configured to compare a frequency difference between the data recovery clock and the clock signal to adjust the frequency of the clock signal based on a comparison result. The signal detecting circuit is coupled to the frequency comparison circuit. The signal detecting circuit is configured to receive and detect the input signal, and the signal detecting circuit determines whether to enable the frequency comparison circuit according to the detection result. Furthermore, a method for generating a data recovery clock is also provided.

公开(公告)号：US09449660B2

公开(公告)日：2016-09-20

申请号：US14309879

申请日：2014-06-19

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jen-Chu Wu ,  An-Chung Chen

IPC: G11C7/22 ,  H03L7/091 ,  H03L7/08 ,  H03L7/081 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/1093 ,  H03L7/0805 ,  H03L7/0812

Abstract: A sampling circuit module, a memory control circuit unit, and a method for sampling data are provided. The sampling circuit module includes a state machine circuit, a first delay line circuit, a second delay line circuit and a delay signal output circuit. In response to a first control signal, the state machine circuit outputs a second control signal and/or a third control signal. The first delay line circuit is configured to receive a reference clock signal and the second control signal to output a first delay clock signal. The second delay line circuit is configured to receive the reference clock signal and the third control signal to output a second delay clock signal. The delay signal output circuit is configured to receive the first delay clock signal and the second delay clock signal to output a third delay clock signal.

Abstract translation: 提供采样电路模块，存储器控制电路单元和数据采样方法。 采样电路模块包括状态机电路，第一延迟线电路，第二延迟线电路和延迟信号输出电路。 响应于第一控制信号，状态机电路输出第二控制信号和/或第三控制信号。 第一延迟线电路被配置为接收参考时钟信号和第二控制信号以输出第一延迟时钟信号。 第二延迟线电路被配置为接收参考时钟信号和第三控制信号以输出第二延迟时钟信号。 延迟信号输出电路被配置为接收第一延迟时钟信号和第二延迟时钟信号以输出第三延迟时钟信号。

公开(公告)号：US09058863B2

公开(公告)日：2015-06-16

申请号：US13871001

申请日：2013-04-26

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Ming Chen ,  An-Chung Chen

IPC: G11C7/22 ,  G11C29/02 ,  G06F13/16

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: A reference frequency setting method of a memory storage apparatus including the following steps is provided. A setting code is read from a memory module or a storage unit by a first signal transmission path and stored into a register circuit. The setting code includes a first setting information. Whether the data having a specific frequency is inputted is detected. If not, the setting code stored in the register circuit is read, such that an oscillator circuit module of the memory storage apparatus generates a first reference frequency based on the first setting information. If yes, the setting code stored in the register circuit is updated by a second signal transmission path, and the updated setting code is read, such that the oscillator circuit module generates a second reference frequency based on a second setting information. The updated setting code includes the second setting information.

Abstract translation: 提供了包括以下步骤的存储器存储装置的参考频率设置方法。 通过第一信号传输路径从存储器模块或存储单元读取设置码并存储到寄存器电路中。 设定代码包括第一设定信息。 检测输入了特定频率的数据。 如果不是，则读取存储在寄存器电路中的设置代码，使得存储器存储设备的振荡器电路模块基于第一设置信息生成第一参考频率。 如果是，则通过第二信号传输路径更新存储在寄存器电路中的设置代码，并且读取更新的设置代码，使得振荡器电路模块基于第二设置信息生成第二参考频率。 更新后的设定代码包括第二设定信息。

公开(公告)号：US09059789B2

公开(公告)日：2015-06-16

申请号：US13863386

申请日：2013-04-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： An-Chung Chen ,  Chih-Ming Chen

IPC: H04B1/00 ,  H04B1/715

CPC classification number: H04B1/715 ,  H04L27/0014 ,  H04L2027/0024 ,  H04L2027/0053

Abstract: A signal processing method, a connector and a memory storage device are provided. The signal processing method is for the connector which does not include a crystal oscillator. The signal processing method includes: receiving a first signal stream from a host system; tracking a transmission frequency of the first signal stream, and obtaining a frequency shift quantity of the first signal stream relative to the transmission frequency; determining if a spread spectrum operation is performed on the first signal stream according to the frequency shift quantity to generate a determination result; generating a second signal stream according to the determination result and the transmission frequency. Accordingly, the spread spectrum operation is handled under the situation without a crystal oscillator.

Abstract translation: 提供信号处理方法，连接器和存储器存储装置。 信号处理方法是用于不包括晶体振荡器的连接器。 信号处理方法包括：从主机系统接收第一信号流; 跟踪第一信号流的传输频率，以及获得第一信号流相对于传输频率的频移量; 根据所述频移量确定是否对所述第一信号流执行扩频操作以产生确定结果; 根据确定结果和传输频率产生第二信号流。 因此，在没有晶体振荡器的情况下处理扩频操作。

公开(公告)号：US09020086B2

公开(公告)日：2015-04-28

申请号：US13851963

申请日：2013-03-28

Applicant: Phison Electronics Corp.

Inventor： Chih-Ming Chen ,  An-Chung Chen

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04L7/04 ,  H03L7/085 ,  H04L7/0054 ,  H04L7/033 ,  H04L7/0331

Abstract: A clock data recovery circuit module including a clock recovery circuit, a frequency comparison circuit and a signal detecting circuit is provided. The clock recovery circuit is configured to output a data recovery stream and a data recovery clock based on an input signal and a clock signal. The frequency comparison circuit is coupled to the clock recovery circuit. The frequency comparison circuit is configured to compare a frequency difference between the data recovery clock and the clock signal to adjust the frequency of the clock signal based on a comparison result. The signal detecting circuit is coupled to the frequency comparison circuit. The signal detecting circuit is configured to receive and detect the input signal, and the signal detecting circuit determines whether to enable the frequency comparison circuit according to the detection result. Furthermore, a method for generating a data recovery clock is also provided.

Abstract translation: 提供了包括时钟恢复电路，频率比较电路和信号检测电路的时钟数据恢复电路模块。 时钟恢复电路被配置为基于输入信号和时钟信号输出数据恢复流和数据恢复时钟。 频率比较电路耦合到时钟恢复电路。 频率比较电路被配置为比较数据恢复时钟和时钟信号之间的频率差，以基于比较结果来调整时钟信号的频率。 信号检测电路耦合到频率比较电路。 信号检测电路被配置为接收和检测输入信号，并且信号检测电路根据检测结果确定是否使能频率比较电路。 此外，还提供了一种用于产生数据恢复时钟的方法。

公开(公告)号：US20180210652A1

公开(公告)日：2018-07-26

申请号：US15456584

申请日：2017-03-13

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Ming Chen ,  An-Chung Chen ,  Kuen-Chih Lin

IPC: G06F3/06

CPC classification number: G06F1/08 ,  G06F13/16

Abstract: An exemplary embodiment of the present disclosure provides a reference clock signal generation method for a memory storage device. The method includes: receiving a first type signal from a host system; generating a first control parameter according to a frequency of the first type signal; receiving a second type signal from the host system after the first type signal is received; generating a second control parameter according to a frequency of the second type signal; and generating a reference clock signal meeting a first condition according to the second control parameter. Therefore, an efficiency of generating the reference clock signal can be improved.

公开(公告)号：US20150311907A1

公开(公告)日：2015-10-29

申请号：US14309879

申请日：2014-06-19

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jen-Chu Wu ,  An-Chung Chen

IPC: H03L7/091 ,  G11C7/22

CPC classification number: G11C7/22 ,  G11C7/1093 ,  H03L7/0805 ,  H03L7/0812

Abstract: A sampling circuit module, a memory control circuit unit, and a method for sampling data are provided. The sampling circuit module includes a state machine circuit, a first delay line circuit, a second delay line circuit and a delay signal output circuit. In response to a first control signal, the state machine circuit outputs a second control signal and/or a third control signal. The first delay line circuit is configured to receive a reference clock signal and the second control signal to output a first delay clock signal. The second delay line circuit is configured to receive the reference clock signal and the third control signal to output a second delay clock signal. The delay signal output circuit is configured to receive the first delay clock signal and the second delay clock signal to output a third delay clock signal.

Abstract translation: 提供采样电路模块，存储器控制电路单元和数据采样方法。 采样电路模块包括状态机电路，第一延迟线电路，第二延迟线电路和延迟信号输出电路。 响应于第一控制信号，状态机电路输出第二控制信号和/或第三控制信号。 第一延迟线电路被配置为接收参考时钟信号和第二控制信号以输出第一延迟时钟信号。 第二延迟线电路被配置为接收参考时钟信号和第三控制信号以输出第二延迟时钟信号。 延迟信号输出电路被配置为接收第一延迟时钟信号和第二延迟时钟信号以输出第三延迟时钟信号。

公开(公告)号：US20140241074A1

公开(公告)日：2014-08-28

申请号：US13871001

申请日：2013-04-26

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Ming Chen ,  An-Chung Chen

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: A reference frequency setting method of a memory storage apparatus including the following steps is provided. A setting code is read from a memory module or a storage unit by a first signal transmission path and stored into a register circuit. The setting code includes a first setting information. Whether the data having a specific frequency is inputted is detected. If not, the setting code stored in the register circuit is read, such that an oscillator circuit module of the memory storage apparatus generates a first reference frequency based on the first setting information. If yes, the setting code stored in the register circuit is updated by a second signal transmission path, and the updated setting code is read, such that the oscillator circuit module generates a second reference frequency based on a second setting information. The updated setting code includes the second setting information.

Abstract translation: 提供了包括以下步骤的存储器存储装置的参考频率设置方法。 通过第一信号传输路径从存储器模块或存储单元读取设置码并存储到寄存器电路中。 设定代码包括第一设定信息。 检测输入了特定频率的数据。 如果不是，则读取存储在寄存器电路中的设置代码，使得存储器存储设备的振荡器电路模块基于第一设置信息生成第一参考频率。 如果是，则通过第二信号传输路径更新存储在寄存器电路中的设置代码，并且读取更新的设置代码，使得振荡器电路模块基于第二设置信息生成第二参考频率。 更新后的设定代码包括第二设定信息。

公开(公告)号：US20140219406A1

公开(公告)日：2014-08-07

申请号：US13851963

申请日：2013-03-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Ming Chen ,  An-Chung Chen

IPC: H04L7/04

CPC classification number: H04L7/04 ,  H03L7/085 ,  H04L7/0054 ,  H04L7/033 ,  H04L7/0331

Abstract: A clock data recovery circuit module including a clock recovery circuit, a frequency comparison circuit and a signal detecting circuit is provided. The clock recovery circuit is configured to output a data recovery stream and a data recovery clock based on an input signal and a clock signal. The frequency comparison circuit is coupled to the clock recovery circuit. The frequency comparison circuit is configured to compare a frequency difference between the data recovery clock and the clock signal to adjust the frequency of the clock signal based on a comparison result. The signal detecting circuit is coupled to the frequency comparison circuit. The signal detecting circuit is configured to receive and detect the input signal, and the signal detecting circuit determines whether to enable the frequency comparison circuit according to the detection result. Furthermore, a method for generating a data recovery clock is also provided.

Abstract translation: 提供了包括时钟恢复电路，频率比较电路和信号检测电路的时钟数据恢复电路模块。 时钟恢复电路被配置为基于输入信号和时钟信号输出数据恢复流和数据恢复时钟。 频率比较电路耦合到时钟恢复电路。 频率比较电路被配置为比较数据恢复时钟和时钟信号之间的频率差，以基于比较结果来调整时钟信号的频率。 信号检测电路耦合到频率比较电路。 信号检测电路被配置为接收和检测输入信号，并且信号检测电路根据检测结果确定是否使能频率比较电路。 此外，还提供了一种用于产生数据恢复时钟的方法。

公开(公告)号：US20140219319A1

公开(公告)日：2014-08-07

申请号：US13863386

申请日：2013-04-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： An-Chung Chen ,  Chih-Ming Chen

IPC: H04B1/715

CPC classification number: H04B1/715 ,  H04L27/0014 ,  H04L2027/0024 ,  H04L2027/0053

Abstract: A signal processing method, a connector and a memory storage device are provided. The signal processing method is for the connector which does not include a crystal oscillator. The signal processing method includes: receiving a first signal stream from a host system; tracking a transmission frequency of the first signal stream, and obtaining a frequency shift quantity of the first signal stream relative to the transmission frequency; determining if a spread spectrum operation is performed on the first signal stream according to the frequency shift quantity to generate a determination result; generating a second signal stream according to the determination result and the transmission frequency. Accordingly, the spread spectrum operation is handled under the situation without a crystal oscillator.

Abstract translation: 提供信号处理方法，连接器和存储器存储装置。 信号处理方法是用于不包括晶体振荡器的连接器。 信号处理方法包括：从主机系统接收第一信号流; 跟踪第一信号流的传输频率，以及获得第一信号流相对于传输频率的频移量; 根据所述频移量确定是否对所述第一信号流执行扩频操作以产生确定结果; 根据确定结果和传输频率产生第二信号流。 因此，在没有晶体振荡器的情况下处理扩频操作。