公开(公告)号：US12236132B2

公开(公告)日：2025-02-25

申请号：US17573567

申请日：2022-01-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Sebastien Jean ,  Ming-Jen Liang

IPC: G06F3/06

Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: sending a first operation command sequence to a rewritable non-volatile memory module to instruct a first memory module in the rewritable non-volatile memory module to perform a first operation; obtaining a first time threshold value corresponding to the first operation; updating a first counting value corresponding to the first memory module; and sending a first query command sequence to the rewritable non-volatile memory module to query a status of the first memory module, in response to that the first counting value reaches the first time threshold value.

公开(公告)号：US20150293809A1

公开(公告)日：2015-10-15

申请号：US14297649

申请日：2014-06-06

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Jen Liang

IPC: G06F11/07

CPC classification number: G06F11/076 ,  G06F3/0614 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0766 ,  G06F11/0793 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246 ,  G06F2212/2022 ,  G11C16/344 ,  G11C29/42 ,  G11C29/52

Abstract: A data storing method, a memory control circuit unit, and a memory storage apparatus are provided. The method includes recording a bit error count of every predetermined area of every physical erasing unit and determining whether the bit error count of one of the predetermined areas of the physical programming unit of the physical erasing unit is more than a threshold bit error count. If the bit error count of one of the predetermined areas of the physical programming unit of the physical erasing unit is more than the threshold bit error count, the method also includes storing data under a second programming mode after an erasing operation is performed on the physical easing unit. Accordingly, defective physical erasing units may be effectively employed to prolong the lifespan of the memory storage apparatus.

Abstract translation: 提供数据存储方法，存储器控制电路单元和存储器存储装置。 该方法包括记录每个物理擦除单元的每个预定区域的位错误计数，并确定物理擦除单元的物理编程单元的预定区域之一的位错误计数是否大于阈值位错误计数。 如果物理擦除单元的物理编程单元的预定区域之一的位错误计数大于阈值位错误计数，则该方法还包括在对物理擦除单元执行擦除操作之后的第二编程模式下存储数据 宽松单位 因此，可以有效地采用有缺陷的物理擦除单元来延长存储器存储装置的使用寿命。

公开(公告)号：US09122498B2

公开(公告)日：2015-09-01

申请号：US13925816

申请日：2013-06-24

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Jen Liang

IPC: G06F12/00 ,  G06F9/445 ,  G06F3/06

CPC classification number: G06F9/445 ,  G06F3/0656 ,  G06F12/00 ,  G06F12/0607 ,  G06F12/0638 ,  G06F2212/1024

Abstract: A firmware code loading method for loading a firmware code from a rewritable non-volatile memory module of a memory storage apparatus is provided. The method includes: obtaining a storage address for storing a first portion firmware code copy corresponding to a first portion of the firmware code in a first memory part; and obtaining a storage address for storing a second portion firmware code copy corresponding to a second portion of the firmware code in a second memory part. The method further includes: using a parallel mode or a interleave mode to load the first portion firmware code copy and the second portion firmware code copy respectively from the first memory part and the second memory part into a buffer memory. Accordingly, the method can effectively shorten the time of loading the firmware code.

Abstract translation: 提供了一种用于从存储器存储装置的可重写非易失性存储器模块加载固件代码的固件代码加载方法。 该方法包括：获得用于存储与第一存储器部分中的固件代码的第一部分相对应的第一部分固件代码拷贝的存储地址; 以及获得用于存储与第二存储器部分中的固件代码的第二部分相对应的第二部分固件代码拷贝的存储地址。 该方法还包括：使用并行模式或交错模式将第一部分固件代码拷贝和第二部分固件代码拷贝分别从第一存储器部分和第二存储器部分加载到缓冲存储器中。 因此，该方法可以有效地缩短加载固件代码的时间。

公开(公告)号：US20140372667A1

公开(公告)日：2014-12-18

申请号：US13958627

申请日：2013-08-05

Applicant: Phison Electronics Corp.

Inventor： Kheng-Chong Tan ,  Ming-Jen Liang

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0679 ,  G06F11/1048 ,  G06F2212/7203

Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes receiving a write command and data corresponding to the write command from a host system and temporarily storing the data into a buffer memory, and the data includes a plurality of sub-data streams. The method still includes transmitting the sub-data streams into the rewritable non-volatile memory module, thereby writing the sub-data streams into at least one physical erasing unit of the rewritable non-volatile memory module. The method further includes generating parity information based on at least portion of the sub-data streams; storing the parity information into the buffer memory and deleting the data from the buffer memory. Accordingly, the method can effectively utilize the storage space of the buffer memory.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的数据写入方法。 该方法包括从主机系统接收写入命令和对应于写入命令的数据，并将数据临时存储到缓冲存储器中，并且数据包括多个子数据流。 该方法还包括将子数据流发送到可重写非易失性存储器模块中，从而将子数据流写入可重写非易失性存储器模块的至少一个物理擦除单元。 该方法还包括基于子数据流的至少一部分产生奇偶校验信息; 将奇偶校验信息存储到缓冲存储器中，并从缓冲存储器中删除数据。 因此，该方法可以有效地利用缓冲存储器的存储空间。

公开(公告)号：US20140337681A1

公开(公告)日：2014-11-13

申请号：US13939191

申请日：2013-07-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Jen Liang

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: A data writing method, a memory storage device, and a memory controller for controlling a rewritable non-volatile memory module are provided. The rewritable non-volatile memory module includes at least one memory chip, and each memory chip includes a plurality of physical erasing units. The data writing method includes following steps. A data is written into at least one first physical erasing unit. A first error correction code and a second error correction code are respectively generated according to the data, where a number of bits correctable to the second error correction code is greater than a number of bits correctable to the first error correction code. The second error correction code is written into a second physical erasing unit. The first physical erasing unit and the second physical erasing unit belong to the same memory chip. Thereby, the memory space can be efficiently used.

Abstract translation: 提供了一种用于控制可重写非易失性存储器模块的数据写入方法，存储器存储装置和存储器控制器。 可重写非易失性存储器模块包括至少一个存储器芯片，并且每个存储器芯片包括多个物理擦除单元。 数据写入方法包括以下步骤。 将数据写入至少一个第一物理擦除单元。 根据数据分别产生第一纠错码和第二纠错码，其中可校正到第二纠错码的比特数大于可纠正到第一纠错码的比特数。 第二纠错码被写入第二物理擦除单元。 第一物理擦除单元和第二物理擦除单元属于相同的存储芯片。 由此，可以有效地使用存储器空间。

公开(公告)号：US11145372B2

公开(公告)日：2021-10-12

申请号：US16285178

申请日：2019-02-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Jen Liang

IPC: G11C16/08 ,  G06F3/06 ,  G11C16/26 ,  G11C16/14 ,  G11C16/24 ,  G11C11/56 ,  G11C16/04

Abstract: The present invention provides a decoding method, a memory controlling circuit unit, and a memory storage device. The decoding method includes: receiving a plurality of commands; reading a first physical programming unit to obtain a plurality of first data respectively by using a plurality of first reading voltage groups of a plurality of reading voltage groups based on a first read command of the plurality of commands and executing a first decoding operation in each of the plurality of first data, wherein a number of the plurality of first reading voltage groups is less than a number of the plurality of reading voltage groups; and executing other commands being different from the first read command of the plurality of commands when unsuccessfully executing the first decoding operation for each of the plurality of first data.

公开(公告)号：US09665480B2

公开(公告)日：2017-05-30

申请号：US14328719

申请日：2014-07-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Jen Liang

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/1016 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The memory management method includes: grouping a plurality of non-spare physical erasing units into a first physical erasing unit and a second physical erasing unit, and a data updating frequency of the first physical erasing unit is lower than the data updating frequency of the second physical erasing unit; selecting a third physical erasing unit from the physical erasing units belonging to the first physical erasing unit; selecting a fourth physical erasing unit from spare physical erasing units, and copying valid data stored in the third physical erasing unit to the fourth physical erasing unit.

公开(公告)号：US09280460B2

公开(公告)日：2016-03-08

申请号：US14226768

申请日：2014-03-26

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Jen Liang

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G06F2003/0697 ,  G06F2212/7205

Abstract: A data writing method for a rewritable non-volatile memory module having a plurality of physical erasing units, and a memory control circuit unit and the memory storage apparatus are provided. The method includes grouping the physical erasing units into at least a data area, a backup area and a spare area; and setting a value obtained by summing a minimum threshold and a predetermined number as a garbage collecting threshold. The data writing method also includes getting at least one physical erasing unit from the spare area, writing data into the gotten physical erasing unit, associating the gotten physical erasing unit with the backup area and re-adjusting the garbage collecting threshold according to the number of physical erasing units associated with the backup area and the minimum threshold.

Abstract translation: 提供一种具有多个物理擦除单元的可重写非易失性存储器模块的数据写入方法，以及存储器控制电路单元和存储器存储装置。 该方法包括将物理擦除单元分组成至少数据区，备份区和备用区; 并且将通过将最小阈值和预定数量相加得到的值设置为垃圾收集阈值。 数据写入方法还包括从备用区域获取至少一个物理擦除单元，将数据写入所获取的物理擦除单元，将获取的物理擦除单元与备份区域相关联，并根据数据的编号重新调整垃圾收集阈值 与备份区域相关联的物理擦除单元和最小阈值。

公开(公告)号：US20150161042A1

公开(公告)日：2015-06-11

申请号：US14160578

申请日：2014-01-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Jen Liang ,  Kheng-Chong Tan

IPC: G06F12/02

CPC classification number: G06F12/0253 ,  G06F12/0246 ,  G06F12/0607 ,  G06F2212/702 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A memory management method, a memory controlling circuit unit and a memory storage device are provided. The method includes: configuring a plurality of super physical erasing units, wherein each of the super physical erasing units includes at least two physical erasing units. A first super physical erasing unit includes a first physical erasing unit and a second physical erasing unit that belong to different operation units. The first physical erasing unit and the second physical erasing unit store different parts of first data. The physical erasing unit storing least valid data from each operation unit is selected for executing a garbage collection procedure. Accordingly, an efficiency of the garbage collection procedure is increased.

Abstract translation: 提供存储器管理方法，存储器控制电路单元和存储器存储装置。 该方法包括：配置多个超级物理擦除单元，其中每个超级物理擦除单元包括至少两个物理擦除单元。 第一超物理擦除单元包括属于不同操作单元的第一物理擦除单元和第二物理擦除单元。 第一物理擦除单元和第二物理擦除单元存储第一数据的不同部分。 选择存储来自每个操作单元的最低有效数据的物理擦除单元用于执行垃圾收集过程。 因此，提高垃圾收集程序的效率。

公开(公告)号：US20140372833A1

公开(公告)日：2014-12-18

申请号：US13957446

申请日：2013-08-02

Applicant: Phison Electronics Corp.

Inventor： Ming-Jen Liang

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1072

Abstract: A data protecting method, a memory controller, and a memory storage device are provided. The data protecting method includes following steps. A first flush command and a first write command instructing to write a first data are received from a host system. A first error correcting code and a corresponding second error correcting code having different protection capabilities are generated according to the first data. A second write command instructing to write a second data is received. After the first write command is received, a second flush command is received from the host system, and the second error correcting code corresponding to the first data is then written into a rewritable non-volatile memory module. A second error correcting code corresponding to the second data is not generated or is generated but not written into the rewritable non-volatile memory module. Thereby, data from the host system is protected.

Abstract translation: 提供数据保护方法，存储器控制器和存储器存储设备。 数据保护方法包括以下步骤。 从主机系统接收到指示写入第一数据的第一刷新命令和第一写命令。 根据第一数据生成具有不同保护能力的第一纠错码和对应的第二纠错码。 接收指示写入第二数据的第二写命令。 在接收到第一写入命令之后，从主机系统接收第二刷新命令，然后将与第一数据相对应的第二纠错码写入可重写的非易失性存储器模块。 对应于第二数据的第二纠错码不产生或产生，而不被写入可重写非易失性存储器模块。 因此，来自主机系统的数据被保护。