公开(公告)号：US09201785B2

公开(公告)日：2015-12-01

申请号：US13958627

申请日：2013-08-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kheng-Chong Tan ,  Ming-Jen Liang

IPC: G06F12/02 ,  G06F11/10 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0679 ,  G06F11/1048 ,  G06F2212/7203

Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes receiving a write command and data corresponding to the write command from a host system and temporarily storing the data into a buffer memory, and the data includes a plurality of sub-data streams. The method still includes transmitting the sub-data streams into the rewritable non-volatile memory module, thereby writing the sub-data streams into at least one physical erasing unit of the rewritable non-volatile memory module. The method further includes generating parity information based on at least portion of the sub-data streams; storing the parity information into the buffer memory and deleting the data from the buffer memory. Accordingly, the method can effectively utilize the storage space of the buffer memory.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的数据写入方法。 该方法包括从主机系统接收写入命令和对应于写入命令的数据，并将数据临时存储到缓冲存储器中，并且数据包括多个子数据流。 该方法还包括将子数据流发送到可重写非易失性存储器模块中，从而将子数据流写入可重写非易失性存储器模块的至少一个物理擦除单元。 该方法还包括基于子数据流的至少一部分产生奇偶校验信息; 将奇偶校验信息存储到缓冲存储器中，并从缓冲存储器中删除数据。 因此，该方法可以有效地利用缓冲存储器的存储空间。

公开(公告)号：US09652378B2

公开(公告)日：2017-05-16

申请号：US13950284

申请日：2013-07-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kuo-Hwa Ho ,  Kheng-Chong Tan

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/1016 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7208

Abstract: A writing method, a memory controller and a memory storage device are provided. The writing method includes steps of: configuring logical addresses to map to part of physical programming units in a storage area, wherein at least one of the physical programming units stores a valid data; transmitting a first write command for writing data having a first data length to at least one of the physical programming units; receiving a status signal; and selecting a spare physical erasing unit and copying the valid data having a second data length to the spare physical erasing unit, after transmitting the first write command and before receiving the status signal, wherein the first data length is not greater than the second data length. Therefore, it prevents a host system from waiting too long when writing data.

公开(公告)号：US20140372667A1

公开(公告)日：2014-12-18

申请号：US13958627

申请日：2013-08-05

Applicant: Phison Electronics Corp.

Inventor： Kheng-Chong Tan ,  Ming-Jen Liang

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0679 ,  G06F11/1048 ,  G06F2212/7203

Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes receiving a write command and data corresponding to the write command from a host system and temporarily storing the data into a buffer memory, and the data includes a plurality of sub-data streams. The method still includes transmitting the sub-data streams into the rewritable non-volatile memory module, thereby writing the sub-data streams into at least one physical erasing unit of the rewritable non-volatile memory module. The method further includes generating parity information based on at least portion of the sub-data streams; storing the parity information into the buffer memory and deleting the data from the buffer memory. Accordingly, the method can effectively utilize the storage space of the buffer memory.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的数据写入方法。 该方法包括从主机系统接收写入命令和对应于写入命令的数据，并将数据临时存储到缓冲存储器中，并且数据包括多个子数据流。 该方法还包括将子数据流发送到可重写非易失性存储器模块中，从而将子数据流写入可重写非易失性存储器模块的至少一个物理擦除单元。 该方法还包括基于子数据流的至少一部分产生奇偶校验信息; 将奇偶校验信息存储到缓冲存储器中，并从缓冲存储器中删除数据。 因此，该方法可以有效地利用缓冲存储器的存储空间。

公开(公告)号：US20140325119A1

公开(公告)日：2014-10-30

申请号：US13950284

申请日：2013-07-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kuo-Hwa Ho ,  Kheng-Chong Tan

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/1016 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7208

Abstract: A writing method, a memory controller and a memory storage device are provided. The writing method includes steps of: configuring logical addresses to map to part of physical programming units in a storage area, wherein at least one of the physical programming units stores a valid data; transmitting a first write command for writing data having a first data length to at least one of the physical programming units; receiving a status signal; and selecting a spare physical erasing unit and copying the valid data having a second data length to the spare physical erasing unit, after transmitting the first write command and before receiving the status signal, wherein the first data length is not greater than the second data length. Therefore, it prevents a host system from waiting too long when writing data.

Abstract translation: 提供了写入方法，存储器控制器和存储器存储装置。 写入方法包括以下步骤：配置逻辑地址以映射到存储区域中的物理编程单元的一部分，其中物理编程单元中的至少一个存储有效数据; 向所述物理编程单元中的至少一个发送用于将具有第一数据长度的数据写入的第一写命令; 接收状态信号; 以及在发送所述第一写入命令之后并且在接收到所述状态信号之前，选择备用物理擦除单元并将具有第二数据长度的有效数据复制到所述备用物理擦除单元，其中所述第一数据长度不大于所述第二数据长度 。 因此，它防止主机系统在写入数据时等待太久。

公开(公告)号：US09996415B2

公开(公告)日：2018-06-12

申请号：US15182609

申请日：2016-06-15

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Jen Liang ,  Kheng-Chong Tan

IPC: G11C29/00 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0631 ,  G06F3/0632 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0679 ,  G11C29/52 ,  G11C29/70

Abstract: A data correcting method for a rewritable non-volatile memory module is provided. The method includes: if a first user data read from a first physical programming unit cannot be corrected by a corresponding first parity code, reading at least one group parity code of a first encoded group that the first physical programming unit belongs to into a buffer, sending the group parity code to a correcting circuit, and reading a user data from physical programming units belonging to the first encoded group into the buffer and sending the user data and the group parity code to the correcting circuit in batches to obtain a corrected first user data corresponding to the first user data.

公开(公告)号：US20150039820A1

公开(公告)日：2015-02-05

申请号：US14520352

申请日：2014-10-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Lai-Hock Chua ,  Kheng-Chong Tan

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0866 ,  G06F2212/214 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C16/102

Abstract: A flash memory storage system having a flash memory controller and a flash memory chip is provided. The flash memory controller configures a second physical unit of the flash memory chip as a midway cache physical unit corresponding to a first physical unit and temporarily stores first data corresponding to a first host write command and second data corresponding to a second host write command in the midway cache physical unit, wherein the first and second data corresponding to slow physical addresses of the first physical unit. Then, the flash memory controller synchronously copies the first and second data from the midway cache physical unit into the first physical unit, thereby shortening time for writing data into the flash memory chip.

Abstract translation: 提供具有闪速存储器控制器和闪速存储器芯片的闪速存储器存储系统。 闪速存储器控制器将闪存芯片的第二物理单元配置为对应于第一物理单元的中途缓存物理单元，并将对应于第一主机写入命令的第一数据和对应于第二主机写命令的第二数据临时存储在 中间缓存物理单元，其中所述第一和第二数据对应于所述第一物理单元的慢物理地址。 然后，闪速存储器控制器将第一和第二数据从中途高速缓存物理单元同步复制到第一物理单元中，从而缩短将数据写入闪存芯片的时间。

公开(公告)号：US20150161042A1

公开(公告)日：2015-06-11

申请号：US14160578

申请日：2014-01-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Jen Liang ,  Kheng-Chong Tan

IPC: G06F12/02

CPC classification number: G06F12/0253 ,  G06F12/0246 ,  G06F12/0607 ,  G06F2212/702 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A memory management method, a memory controlling circuit unit and a memory storage device are provided. The method includes: configuring a plurality of super physical erasing units, wherein each of the super physical erasing units includes at least two physical erasing units. A first super physical erasing unit includes a first physical erasing unit and a second physical erasing unit that belong to different operation units. The first physical erasing unit and the second physical erasing unit store different parts of first data. The physical erasing unit storing least valid data from each operation unit is selected for executing a garbage collection procedure. Accordingly, an efficiency of the garbage collection procedure is increased.

Abstract translation: 提供存储器管理方法，存储器控制电路单元和存储器存储装置。 该方法包括：配置多个超级物理擦除单元，其中每个超级物理擦除单元包括至少两个物理擦除单元。 第一超物理擦除单元包括属于不同操作单元的第一物理擦除单元和第二物理擦除单元。 第一物理擦除单元和第二物理擦除单元存储第一数据的不同部分。 选择存储来自每个操作单元的最低有效数据的物理擦除单元用于执行垃圾收集过程。 因此，提高垃圾收集程序的效率。

公开(公告)号：US20170300379A1

公开(公告)日：2017-10-19

申请号：US15182609

申请日：2016-06-15

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Jen Liang ,  Kheng-Chong Tan

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0631 ,  G06F3/0632 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0679 ,  G11C29/52 ,  G11C29/70

Abstract: A data correcting method for a rewritable non-volatile memory module is provided. The method includes: if a first user data read from a first physical programming unit cannot be corrected by a corresponding first parity code, reading at least one group parity code of a first encoded group that the first physical programming unit belongs to into a buffer, sending the group parity code to a correcting circuit, and reading a user data from physical programming units belonging to the first encoded group into the buffer and sending the user data and the group parity code to the correcting circuit in batches to obtain a corrected first user data corresponding to the first user data.

公开(公告)号：US09009399B2

公开(公告)日：2015-04-14

申请号：US14520352

申请日：2014-10-22

Applicant: Phison Electronics Corp.

Inventor： Lai-Hock Chua ,  Kheng-Chong Tan

IPC: G06F12/00 ,  G06F12/02 ,  G11C16/10 ,  G06F12/08

CPC classification number: G06F12/0246 ,  G06F12/0866 ,  G06F2212/214 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C16/102

Abstract: A flash memory storage system having a flash memory controller and a flash memory chip is provided. The flash memory controller configures a second physical unit of the flash memory chip as a midway cache physical unit corresponding to a first physical unit and temporarily stores first data corresponding to a first host write command and second data corresponding to a second host write command in the midway cache physical unit, wherein the first and second data corresponding to slow physical addresses of the first physical unit. Then, the flash memory controller synchronously copies the first and second data from the midway cache physical unit into the first physical unit, thereby shortening time for writing data into the flash memory chip.

Abstract translation: 提供具有闪速存储器控制器和闪速存储器芯片的闪速存储器存储系统。 闪速存储器控制器将闪存芯片的第二物理单元配置为对应于第一物理单元的中途缓存物理单元，并将对应于第一主机写入命令的第一数据和对应于第二主机写命令的第二数据临时存储在 中间缓存物理单元，其中所述第一和第二数据对应于所述第一物理单元的慢物理地址。 然后，闪速存储器控制器将第一和第二数据从中途高速缓存物理单元同步复制到第一物理单元中，从而缩短将数据写入闪存芯片的时间。

公开(公告)号：US20140289451A1

公开(公告)日：2014-09-25

申请号：US13896328

申请日：2013-05-17

Applicant: Phison Electronics Corp.

Inventor： Kuo-Hwa Ho ,  Kheng-Chong Tan

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: A method of recording mapping information for a rewritable non-volatile memory module is provided. The method includes configuring a plurality of logical addresses, establishing at least one logical address mapping table, and storing the at least one logical address mapping table into the rewritable non-volatile memory module. The method also includes receiving data to be stored into a plurality of continuous logical addresses from a host system, writing the data into a plurality of physical programming units, updating mapping relations between the continuous logical addresses and the physical programming units in a corresponding logical address mapping table loaded to a buffer memory, storing a continuous mapping table in the buffer memory, and recording a continuous mapping record corresponding to the continuous logical addresses in the continuous mapping table.

Abstract translation: 提供了一种用于记录可重写非易失性存储器模块的映射信息的方法。 该方法包括配置多个逻辑地址，建立至少一个逻辑地址映射表，以及将至少一个逻辑地址映射表存储到可重写非易失性存储器模块中。 该方法还包括从主机系统接收要存储到多个连续逻辑地址中的数据，将数据写入多个物理编程单元中，在对应的逻辑地址中更新连续逻辑地址与物理编程单元之间的映射关系 映射表加载到缓冲存储器中，将连续映射表存储在缓冲存储器中，并且在连续映射表中记录与连续逻辑地址相对应的连续映射记录。