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公开(公告)号：US20170332023A1
公开(公告)日：2017-11-16
申请号：US15151078
申请日：2016-05-10
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Roger PANICACCI , Marko MLINAR
CPC classification number: H04N5/3592 , H04N5/3745 , H04N5/378 , H04N9/045 , H04N2209/045
Abstract: An image sensor may include an array of image sensor pixels. Each image sensor pixel may have signal storage capabilities implemented through a write-back supply line and a control transistor for the supply line. Each image sensor pixel may output pixel values over column lines to switching circuitry. The switching circuitry may route the pixel values to signal processing circuitry. The signal processing circuitry may perform analog and/or digital processing operations utilizing analog circuits or pinned diode devices for image signal processing on the pixel values to output processed pixel values. The processing circuitry may send the processed pixel values back to the array. This allows the array to act as memory circuitry to support processing operations on processing circuitry in close proximity to the array. Configured this way, signal processing can be performed in close proximity to the array without having to move pixel signals to peripheral processing circuitry.
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公开(公告)号：US20210136274A1
公开(公告)日：2021-05-06
申请号：US16672256
申请日：2019-11-01
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Roger PANICACCI
Abstract: An image sensor system may include an array of image sensor pixels. A portion of the image sensor array that includes high dynamic range (HDR) content may be oversampled at a higher rate than the rest of the array to generate multiple sub-frames. When reading out the multiple sub-frames, the charge transfer gate pulse may only be partially asserted so that only a part of the full well charge is drained. Partially asserting the charge transfer gate pulse allows drainage of the high light signals without perturbing the low light signals. The last sub-frame should be read out by fully asserting the charge transfer gate pulse to ensure than the entire well charge is drained. Data collected from the multiple sub-frames may be accumulated using digital accumulation circuitry. The rest of the array can be read out at the nominal frame rate.
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公开(公告)号：US20170352696A1
公开(公告)日：2017-12-07
申请号：US15175957
申请日：2016-06-07
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Roger PANICACCI
IPC: H01L27/146 , H03M1/12
CPC classification number: H01L27/14643 , G01J1/4228 , G01J2001/446 , H01L27/14609 , H03M1/1245 , H03M1/468 , H03M1/56 , H03M3/438 , H03M3/456
Abstract: An image sensor may include an array of image pixels coupled to analog-to-digital conversion circuitry formed from pinned photodiode charge transfer circuits. Majority charge carriers for the pinned photodiodes in the charge transfer circuits may be electrons for photodiode wells formed from n-type doped regions and may be holes for photodiode formed from p-type doped regions. Pinned photodiodes may be used for charge integration onto a capacitive circuit node. Pinned photodiodes may also be used for charge subtraction from a capacitive circuit node. Comparator circuitry may be used to determine digital values for the pixel output levels in accordance with single-slope conversion, successive-approximation-register conversion, cyclic conversion, and first or second order delta-sigma conversion techniques. The array of image pixels used for imaging may have a conversion mode wherein at least a portion of the pixel circuitry in the array are operated similar to the charge transfer circuits.
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公开(公告)号：US20210051290A1
公开(公告)日：2021-02-18
申请号：US16854057
申请日：2020-04-21
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Roger PANICACCI , Tim W. CHAN
IPC: H04N5/372 , H04N5/369 , H01L27/146
Abstract: Imaging circuitry may include circuits for implementing feature extraction in the analog domain. The imaging circuitry may include pixels configured to generate pixel values. The pixel values may then be weighted using variable charge integration times, variable resistors in the readout path, and/or variable switch on times in the readout path. The weighted pixels values may be binned and combined to obtain an output neuron voltage for at least one layer in a neural network. Performing feature extraction in the analog domain for each layer of results in the neural network saves power and area by avoiding the need to move data around to conventional digital memories.
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公开(公告)号：US20180274975A1
公开(公告)日：2018-09-27
申请号：US15992853
申请日：2018-05-30
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Roger PANICACCI
CPC classification number: G01J1/4228 , G01J1/44 , G01J2001/446 , H04N5/378
Abstract: An image sensor may include an array of image pixels coupled to analog-to-digital conversion circuitry formed from pinned photodiode charge transfer circuits. Majority charge carriers for the pinned photodiodes in the charge transfer circuits may be electrons for photodiode wells formed from n-type doped regions and may be holes for photodiode formed from p-type doped regions. Pinned photodiodes may be used for charge integration onto a capacitive circuit node. Pinned photodiodes may also be used for charge subtraction from a capacitive circuit node. Comparator circuitry may be used to determine digital values for the pixel output levels in accordance with single-slope conversion, successive-approximation-register conversion, cyclic conversion, and first or second order delta-sigma conversion techniques. The array of image pixels used for imaging may have a conversion mode wherein at least a portion of the pixel circuitry in the array are operated similar to the charge transfer circuits.
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Patent Agency Ranking
公开(公告)号：US20210058580A1
公开(公告)日：2021-02-25
申请号：US15929733
申请日：2020-05-19
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Roger PANICACCI
Abstract: Imaging circuitry may include circuits for implementing feature extraction. The imaging circuitry may include pixels configured to generate pixel values. The pixel values may be optionally scaled by kernel weighting factors. The pixels may be coupled together via a source follower drain path, and a source follower gate in one of the pixels may be selected for readout by coupling that source follower gate to an integrator circuit to compute a feature result. Multiple feature results may be computed successively to detect an event change in either the digital domain or the analog domain. Such feature detection schemes may be applied to detect horizontally-oriented features, vertically-oriented features, diagonally-oriented features, or irregularly shaped features.
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公开(公告)号：US20170352694A1
公开(公告)日：2017-12-07
申请号：US15175960
申请日：2016-06-07
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Roger PANICACCI
IPC: H01L27/146 , H03M1/12
CPC classification number: H01L27/14609 , H01L27/14643 , H03M1/1245 , H03M1/468 , H03M1/56 , H03M3/438 , H03M3/456
Abstract: An image sensor may include an array of image pixels coupled to analog-to-digital conversion circuitry formed from pinned photodiode charge transfer circuits. Majority charge carriers for the pinned photodiodes in the charge transfer circuits may be electrons for photodiode wells formed from n-type doped regions and may be holes for photodiode formed from p-type doped regions. Pinned photodiodes may be used for charge integration onto a capacitive circuit node. Pinned photodiodes may also be used for charge subtraction from a capacitive circuit node. Comparator circuitry may be used to determine digital values for the pixel output levels in accordance with single-slope conversion, successive-approximation-register conversion, cyclic conversion, and first or second order delta-sigma conversion techniques. The array of image pixels used for imaging may have a conversion mode wherein at least a portion of the pixel circuitry in the array are operated similar to the charge transfer circuits.
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公开(公告)号：US20210075986A1
公开(公告)日：2021-03-11
申请号：US16947017
申请日：2020-07-15
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Roger PANICACCI
Abstract: Imaging circuitry may include an array of pixels for capturing an image. A subset of the pixels in the array may be selected to perform depth sensing using region of interest (ROI) switching circuitry incorporated within an intermediate die that is stacked between a top image sensor die in which the array of pixels are formed and a bottom digital processing die. The imaging circuitry may be further provided with depth sensing circuitry having a current memory circuit, a current integrator circuit, a time-to-digital converter, and a loading circuit to compute a time of flight for a laser pulse by sensing changes in the pixel source follower gate current. Such depth sensing schemes may be applied to sense horizontally-oriented features, vertically-oriented features, diagonally-oriented features, or irregularly shaped features.
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公开(公告)号：US20210051287A1
公开(公告)日：2021-02-18
申请号：US16827960
申请日：2020-03-24
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Roger PANICACCI , Tim CHAN
IPC: H04N5/369 , H04N5/378 , H04N5/3745
Abstract: Imaging circuitry may include circuits for implementing current or voltage mode feature extraction in the analog domain. The imaging circuitry may include pixels configured to generate pixel values. The pixel values may then be weighted using adjustable weighting circuits to generate corresponding weighted pixel values. The adjustable weighting circuits may be selectively coupled to the floating diffusion node in each pixel. The weighted pixels values may then be combined to obtain an output neuron voltage for at least one layer in a neural network. Performing feature extraction in the analog domain for each layer of results in the neural network saves power and area by avoiding the need to move data around to conventional digital memories.
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10.发明申请公开(公告)号：US20210051284A1
公开(公告)日：2021-02-18
申请号：US16821767
申请日：2020-03-17
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Roger PANICACCI , Tomas GEURTS
Abstract: Imaging circuitry may include circuits for implementing charge mode feature extraction in the analog domain. The imaging circuitry may include pixels configured to generate pixel values. The pixel values may then be weighted using adjustable weighting circuits to generate corresponding weighted pixel values. The weighted pixels values may then be combined to obtain an output neuron voltage for at least one layer in a neural network. The output neuron voltage may be stored in idle pixels, may be combined with other weighted pixel values, and may be otherwise manipulated prior to being processed in the digital domain. Performing feature extraction in the analog domain for each layer of results in the neural network saves power and area by avoiding the need to move data around to conventional digital memories.
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