公开(公告)号：US12094727B2

公开(公告)日：2024-09-17

申请号：US17568167

申请日：2022-01-04

Applicant: Silicon Motion, Inc.

Inventor： Yi-Hung Chien ,  Chun-Ying Wang ,  Te-Wei Chen ,  Hsiu-Yuan Chen ,  Bing-Ling Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L21/4878 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/565 ,  H01L21/561 ,  H01L24/95

Abstract: A method forming a semiconductor package device includes: providing a substrate; forming a flip chip die on a first side on the substrate; and forming a molding compound on the first side of the substrate. The molding compound covers the flip chip die. The method further includes forming a heat sink on the molding compound; and forming a taping layer on a second side of the substrate, wherein the second side is opposite from the first side in a vertical direction. After forming the taping layer, the method further includes performing a pre-cut process and an etching process on the heat sink; and removing the taping layer.

公开(公告)号：US09991196B2

公开(公告)日：2018-06-05

申请号：US15435398

申请日：2017-02-17

Applicant: Silicon Motion, Inc.

Inventor： Shu-Ying Huang ,  Te-Wei Chen ,  Hsiu-Yuan Chen

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H05K3/00 ,  H05K3/24

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49805 ,  H01L24/97 ,  H05K3/0097 ,  H05K3/242 ,  H05K2201/09681 ,  H05K2203/072 ,  H05K2203/0723

Abstract: The present invention provides a printed circuit board fabricated by a Non-Plating Process that includes at least one plating bar disposed around at least one package unit of the printed circuit board. The package unit includes at least one ground line, at least one power line and a plurality of signal lines. The ground line has a first contact pad exposed on a surface of the printed circuit board, and at least one of the ground lines is connected to the plating bar. The power line has a second contact pad exposed on the surface, and at least one of the power lines is connected to the neighboring plating bar. The signal line has a third contact pad exposed on the surface.

公开(公告)号：US10859630B2

公开(公告)日：2020-12-08

申请号：US15813553

申请日：2017-11-15

Applicant: Silicon Motion, Inc.

Inventor： Hung-Sen Kuo ,  Te-Wei Chen ,  Hung-Sheng Chang ,  Ming-Wan Kuan

IPC: G01R31/319 ,  G01R31/3183 ,  G01R31/28 ,  G01R31/30 ,  G01R31/3177

Abstract: A circuit test method for a test device to test a device under test is provided. The circuit test method includes the steps of applying zero volts to a plurality of power pins of the device under test; applying a test voltage to a first signal pin among a plurality of signal pins of the device under test; and measuring a current on a second signal pin among the plurality of signal pins of the device under test and determining whether there is a leakage current in the device under test.

公开(公告)号：US09312691B2

公开(公告)日：2016-04-12

申请号：US14317166

申请日：2014-06-27

Applicant: Silicon Motion, Inc.

Inventor： Te-Wei Chen

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: The present invention provides an ESD protection circuit including a discharge transistor, a first switch, a second switch, a third switch and a fourth switch. The discharge transistor forms a discharge path between a first voltage terminal and a second voltage terminal. The first switch selectively provides voltage at the first voltage terminal to a control terminal of the discharge transistor. The second switch selectively provides voltage at the second voltage terminal to the control terminal of the discharge transistor. The third switch selectively provides voltage at the first voltage terminal to a substrate of the discharge transistor. The fourth switch selectively provides voltage at second voltage terminal to the substrate of the discharge transistor.

Abstract translation: 本发明提供一种包括放电晶体管，第一开关，第二开关，第三开关和第四开关的ESD保护电路。 放电晶体管在第一电压端子和第二电压端子之间形成放电路径。 第一开关选择性地将第一电压端子处的电压提供给放电晶体管的控制端子。 第二开关选择性地将第二电压端子处的电压提供给放电晶体管的控制端子。 第三开关选择性地将第一电压端子处的电压提供给放电晶体管的衬底。 第四开关选择性地将第二电压端子处的电压提供给放电晶体管的衬底。