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    WAFER ALIGNMENT STRUCTURE
    1.
    发明公开
    WAFER ALIGNMENT STRUCTURE 审中-公开

    公开(公告)号：US20240234333A9

    公开(公告)日：2024-07-11

    申请号：US18548433

    申请日：2022-02-23

    Applicant: Tesla, Inc.

    Inventor： Yong guo Li ,  Rishabh Bhandari ,  Aydin Nabovati ,  Ron Rosenberg ,  Vijaykumar Krithivasan ,  Mitchell Heschke

    IPC: H01L23/544 ,  H01L23/367

    CPC classification number: H01L23/544 ,  H01L23/367 ,  H01L2223/54426

    Abstract: A system on a wafer (SoW) assembly is disclosed. The SoW assembly can include a first SoW assembly structure with a first coefficient of thermal expansion (CTE). The first SoW assembly structure includes first to third slots at different locations. The SoW assembly can include a second SoW assembly structure stacked on the first SoW assembly structure. The second SoW assembly structure has a second CTE different from the first CTE. The second SoW assembly structure has first to third pins extending therefrom and disposed in the first to third slots. The first and second slots shaped to allow the first and second pins to move along a first axis, and the third slot shaped to allow the third pin to move along a second axis. The first SoW assembly structure can be a SoW and the second SoW assembly structure can be a heat dissipation structure in certain applications.

    ELECTRONIC ASSEMBLIES AND METHODS OF MANUFACTURING THE SAME
    3.
    发明公开
    ELECTRONIC ASSEMBLIES AND METHODS OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240312863A1

    公开(公告)日：2024-09-19

    申请号：US18576230

    申请日：2022-06-28

    Applicant: Tesla, Inc.

    Inventor： Yong guo Li ,  Rishabh Bhandari ,  Aydin Nabovati ,  Vijaykumar Krithivasan ,  William Chang

    IPC: H01L23/367 ,  H01L21/48 ,  H01L23/40

    CPC classification number: H01L23/3675 ,  H01L21/4882 ,  H01L23/40

    Abstract: Wafer assemblies and related methods of manufacture are disclosed. Such assemblies and methods can account for different heights of electronic modules positioned on a wafer. In an embodiment, a wafer assembly includes a cooling system, a wafer, a first electronic module, a second electronic module, and a height adjustment structure. A first thermal interface material (TIM) can be disposed between the first electronic module and a first portion of the cooling system. A second TIM can be disposed between the second electronic module and a second portion of the cooling system. The height adjustment structure can compensate for a height difference between the first electronic module and the second electronic module. Other wafer assemblies and methods of manufacture are disclosed.

    SANDWICHED MULTI-LAYER STRUCTURE FOR COOLING HIGH POWER ELECTRONICS
    5.
    发明申请
    SANDWICHED MULTI-LAYER STRUCTURE FOR COOLING HIGH POWER ELECTRONICS 有权

    公开(公告)号：US20250087557A1

    公开(公告)日：2025-03-13

    申请号：US18580580

    申请日：2022-08-16

    Applicant: Tesla, Inc.

    Inventor： Aydin Nabovati ,  Mitchell Heschke ,  Zheng Gao ,  Vijaykumar Krithivasan ,  Mohamed Haitham Helmy Nasr

    IPC: H01L23/473 ,  H01L25/065

    Abstract: The systems, methods, and devices disclosed herein relate to sandwiched multi-layer structures for cooling electronics. In some embodiments, a computing assembly can include a first cooling system, a first electronics layer, a second cooling system, and a second electronics layer. The first cooling system can be disposed on top of and can be in thermal communication with the first electronics layer, the first electronics layer can be disposed on top of and can be in thermal communication with the second cooling system, and the second cooling system can be disposed on top of and can be in thermal communication with the second electronics layer. In some embodiments, at least one layer can use system on wafer packaging.

    WAFER ALIGNMENT STRUCTURE
    7.
    发明公开
    WAFER ALIGNMENT STRUCTURE 审中-公开

    公开(公告)号：US20240136303A1

    公开(公告)日：2024-04-25

    申请号：US18548433

    申请日：2022-02-23

    Applicant: Tesla, Inc.

    Inventor： Yong guo Li ,  Rishabh Bhandari ,  Aydin Nabovati ,  Ron Rosenberg ,  Vijaykumar Krithivasan ,  Mitchell Heschke

    IPC: H01L23/544 ,  H01L23/367

    CPC classification number: H01L23/544 ,  H01L23/367 ,  H01L2223/54426

    Abstract: A system on a wafer (SoW) assembly is disclosed. The SoW assembly can include a first SoW assembly structure with a first coefficient of thermal expansion (CTE). The first SoW assembly structure includes first to third slots at different locations. The SoW assembly can include a second SoW assembly structure stacked on the first SoW assembly structure. The second SoW assembly structure has a second CTE different from the first CTE. The second SoW assembly structure has first to third pins extending therefrom and disposed in the first to third slots. The first and second slots shaped to allow the first and second pins to move along a first axis, and the third slot shaped to allow the third pin to move along a second axis. The first SoW assembly structure can be a SoW and the second SoW assembly structure can be a heat dissipation structure in certain applications.

    VOLTAGE REGULATING MODULE DESIGN FOR THE USE OF UNDERFILL
    8.
    发明公开
    VOLTAGE REGULATING MODULE DESIGN FOR THE USE OF UNDERFILL 审中-公开

    公开(公告)号：US20240061482A1

    公开(公告)日：2024-02-22

    申请号：US18260216

    申请日：2022-01-20

    Applicant: Tesla, Inc.

    Inventor： Vijaykumar Krithivasan ,  Samuel Lichy ,  Yong guo Li

    IPC: G06F1/26 ,  H01L23/498 ,  H01L23/367 ,  H01L25/18 ,  H01L23/00

    CPC classification number: G06F1/26 ,  H01L23/49816 ,  H01L23/367 ,  H01L25/18 ,  H01L23/562

    Abstract: A voltage regulating module design is provided. In one aspect, a voltage regulating module (VRM) includes a first layer configured to output a regulated voltage that is based on a stepped down voltage, and a second layer stacked with the first layer, and a plurality of contacts, such as a ball grid array (BGA), on the first layer. The second layer includes a plurality of active components configured to provide the stepped down voltage to the first layer. The first and second layers have overlapping recesses, and the recess of the first layer has a larger footprint than the recess of the second layer. A plurality of the VRMS can be arranged to form an opening including a counterbore. A faster, such as a bolt, can be positioned in the opening. The first layer can have a larger clearance from the fastener positioned in the opening than the second layer.

    Packaged device having imbedded array of components
    10.
    发明授权
    Packaged device having imbedded array of components 有权

    公开(公告)号：US11122678B2

    公开(公告)日：2021-09-14

    申请号：US16735573

    申请日：2020-01-06

    Applicant: Tesla, Inc.

    Inventor： Vijaykumar Krithivasan ,  Jin Zhao ,  Mengzhi Pang ,  Steven Wayne Butler ,  Ganesh Venkataramanan ,  Yang Sun

    IPC: H05K1/02 ,  H01L23/00 ,  H05K3/30

    Abstract: A structure having imbedded array of components is described. An example structure includes an imbedded component array layer having an array of imbedded passive devices contained therein. The structure further includes an Integrated Fan-Out (InFO) layer residing adjacent a first surface of the imbedded component array layer having traces and vias formed therein. The structure further includes an insulator layer residing adjacent a second surface of the imbedded component array layer and electrically coupled to at least the InFO layer and vias passing through the imbedded component array layer and electrically coupled to some of vias of the InFO layer.

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