公开(公告)号：US20250149440A1

公开(公告)日：2025-05-08

申请号：US18393771

申请日：2023-12-22

Applicant: United Microelectronics Corp.

Inventor： Chien-Yi LEE ,  Tse-Pu Chen ,  Yi-Chin Li ,  Sheng-Huei Dai

IPC: H01L23/522 ,  H01L29/94

Abstract: An electronic device including a substrate with a trench and an inductor disposed on the substrate is provided. The inductor includes a first conductive layer and a second conductive layer. The first conductive layer is conformally disposed on the substrate. At least a portion of the first conductive layer is disposed in the trench. The first conductive layer has a first end portion and a second end portion. The second conductive layer is conformally disposed on the first conductive layer. The second conductive layer has a first end portion and a second end portion on the first end portion of the first conductive layer and the second end portion of the first conductive layer, respectively. The first end portion of the second conductive layer is electrically connected with the second end portion of the first conductive layer.

公开(公告)号：US20140252482A1

公开(公告)日：2014-09-11

申请号：US14288369

申请日：2014-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rai-Min Huang ,  Sheng-Huei Dai ,  Chen-Hua Tsai ,  Duan Quan Liao ,  Yikun Chen ,  Xiao Zhong Zhu

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: A FINFET transistor structure includes a substrate including a fin structure. Two combined recesses embedded within the substrate, wherein each of the combined recesses includes a first recess extending in a vertical direction and a second recess extending in a lateral direction, the second recess has a protruding side extending to and under the fin structure. Two filling layers respectively fill in the combined recesses. A gate structure crosses the fin structure.

Abstract translation: FINFET晶体管结构包括包括鳍结构的衬底。 嵌入在基板内的两个组合的凹槽，其中每个组合的凹槽包括沿垂直方向延伸的第一凹部和沿横向方向延伸的第二凹槽，第二凹部具有延伸到翅片结构下方和下方的突出侧。 两个填充层分别填充组合的凹部。 栅极结构穿过鳍结构。

公开(公告)号：US09331161B1

公开(公告)日：2016-05-03

申请号：US14554068

申请日：2014-11-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Ju Lee ,  Yao-Chang Wang ,  Nien-Ting Ho ,  Chi-Mao Hsu ,  Kuan-Cheng Su ,  Main-Gwo Chen ,  Hsiao-Kwang Yang ,  Fang-Hong Yao ,  Sheng-Huei Dai ,  Tzung-Lin Li

IPC: H01L21/02 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02194 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/78

Abstract: The present invention provides a metal gate structure which is formed in a trench of a dielectric layer. The metal gate structure includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench and comprises a bottom portion and a side portion, wherein a ratio between a thickness of the bottom portion and a thickness of the side portion is between 2 and 5. The trench is filled with the metal layer. The present invention further provides a method of forming the metal gate structure.

Abstract translation: 本发明提供了形成在电介质层的沟槽中的金属栅极结构。 金属栅极结构包括功函数金属层和金属层。 工作功能金属层设置在沟槽中，并且包括底部和侧部，其中底部的厚度和侧部的厚度之间的比率在2-5之间。沟槽填充有金属 层。 本发明还提供一种形成金属栅极结构的方法。

公开(公告)号：US20180358351A1

公开(公告)日：2018-12-13

申请号：US15621772

申请日：2017-06-13

Applicant: United Microelectronics Corp.

Inventor： Sheng-Huei Dai ,  Tzung-Lin Li

IPC: H01L27/02 ,  H01L29/66

CPC classification number: H01L27/0255 ,  H01L27/0288 ,  H01L29/66136 ,  H01L29/66174 ,  H01L29/94

Abstract: A protection device as provided includes a doped well with a first-type impurity, formed in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage.

公开(公告)号：US20160126331A1

公开(公告)日：2016-05-05

申请号：US14554068

申请日：2014-11-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Ju Lee ,  Yao-Chang Wang ,  Nien-Ting Ho ,  Chi-Mao Hsu ,  Kuan-Cheng Su ,  Main-Gwo Chen ,  Hsiao-Kwang Yang ,  Fang-Hong Yao ,  Sheng-Huei Dai ,  Tzung-Lin Li

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/42376 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02194 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/78

Abstract: The present invention provides a metal gate structure which is formed in a trench of a dielectric layer. The metal gate structure includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench and comprises a bottom portion and a side portion, wherein a ratio between a thickness of the bottom portion and a thickness of the side portion is between 2 and 5. The trench is filled with the metal layer. The present invention further provides a method of forming the metal gate structure.

Abstract translation: 本发明提供了形成在电介质层的沟槽中的金属栅极结构。 金属栅极结构包括功函数金属层和金属层。 工作功能金属层设置在沟槽中，并且包括底部和侧部，其中底部的厚度和侧部的厚度之间的比率在2-5之间。沟槽填充有金属 层。 本发明还提供一种形成金属栅极结构的方法。

公开(公告)号：US09406805B2

公开(公告)日：2016-08-02

申请号：US14749648

申请日：2015-06-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hua Tsai ,  Rai-Min Huang ,  Sheng-Huei Dai ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L21/02 ,  H01L21/20

CPC classification number: H01L29/7853 ,  H01L21/02647 ,  H01L21/2022 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785 ,  H01L2029/7858

Abstract: A Fin-FET and a method of forming the Fin-FET are provided. A substrate is provided, and then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.

公开(公告)号：US09385193B2

公开(公告)日：2016-07-05

申请号：US14288369

申请日：2014-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rai-Min Huang ,  Sheng-Huei Dai ,  Chen-Hua Tsai ,  Duan Quan Liao ,  Yikun Chen ,  Xiao Zhong Zhu

IPC: H01L29/06 ,  H01L27/108 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: A FINFET transistor structure includes a substrate including a fin structure. Two combined recesses embedded within the substrate, wherein each of the combined recesses includes a first recess extending in a vertical direction and a second recess extending in a lateral direction, the second recess has a protruding side extending to and under the fin structure. Two filling layers respectively fill in the combined recesses. A gate structure crosses the fin structure.

Abstract translation: FINFET晶体管结构包括包括鳍结构的衬底。 嵌入在基板内的两个组合的凹槽，其中每个组合的凹槽包括沿垂直方向延伸的第一凹部和沿横向方向延伸的第二凹槽，第二凹部具有延伸到翅片结构下方和下方的突出侧。 两个填充层分别填充组合的凹部。 栅极结构穿过鳍结构。

公开(公告)号：US20240186271A1

公开(公告)日：2024-06-06

申请号：US18094397

申请日：2023-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Yi Lee ,  Sheng-Huei Dai ,  Chen-Wei Pan

IPC: H01L23/66 ,  H01Q15/24

CPC classification number: H01L23/66 ,  H01Q15/24 ,  H01L2223/6605 ,  H01L2223/6688

Abstract: A radiofrequency filter includes a substrate, an isolation structure, an electrically conductive structure, a spacer structure, a dielectric layer, a patterned electrically conductive film, a first contact structure, and a second contact structure. The isolation structure is disposed in the substrate. The electrically conductive structure is disposed on the isolation structure. The spacer structure is disposed on the substrate and located on a sidewall of the electrically conductive structure. The dielectric layer is disposed on the electrically conductive structure. The patterned electrically conductive film is disposed on the dielectric layer. At least a part of the dielectric layer is located between the electrically conductive structure and the patterned electrically conductive film in a vertical direction. The first contact structure and the second contact structure are disposed on and electrically connected with the patterned electrically conductive film.

公开(公告)号：US20190148356A1

公开(公告)日：2019-05-16

申请号：US16248615

申请日：2019-01-15

Applicant: United Microelectronics Corp.

Inventor： Sheng-Huei Dai ,  Tzung-Lin Li

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/861

Abstract: A method for fabricating a protection device includes forming a doped well with a first-type impurity in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage.

公开(公告)号：US10262986B2

公开(公告)日：2019-04-16

申请号：US15621772

申请日：2017-06-13

Applicant: United Microelectronics Corp.

Inventor： Sheng-Huei Dai ,  Tzung-Lin Li

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/94

Abstract: A protection device as provided includes a doped well with a first-type impurity, formed in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage.