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公开(公告)号：US11789860B2
公开(公告)日：2023-10-17
申请号：US17694470
申请日：2022-03-14
Applicant: Western Digital Technologies, Inc.
Inventor： Amir Hossein Gholamipour , Mark David Myran , Chandan Mishra , Namhoon Yoo , Jun Tao
IPC: G06F11/00 , G06F12/00 , G06F12/02 , G06F11/14 , G06F12/0804
CPC classification number: G06F12/0246 , G06F11/1441 , G06F11/1471 , G06F12/0804 , G06F2201/81 , G06F2201/84 , G06F2212/1024 , G06F2212/7201 , G06F2212/7203
Abstract: Disclosed are systems and methods for providing logical to physical (L2P) table management using low-latency NVM to reduce solid state drive (SSD) random access memory (RAM) footprint. A method includes determining a logical to physical (L2P) mapping of a logical address to a physical address in a flash storage, for an operation directed to the logical address. The method also includes adding a data entry, comprising the L2P mapping, to an open journal structure in RAM. The method also includes adding a log entry, comprising the L2P mapping, to a buffer in the RAM. The method also includes flushing the buffer to a low-latency NVM storage in response to determining that the buffer has satisfied a size threshold. Reads, snapshotting and L2P table recovery are also described.
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公开(公告)号：US11557352B2
公开(公告)日：2023-01-17
申请号：US17244794
申请日：2021-04-29
Applicant: Western Digital Technologies, Inc.
Inventor： Niang-Chu Chen , Jun Tao
IPC: G11C16/26 , G11C16/08 , G11C11/56 , G11C11/408 , G11C29/42 , G11C29/52 , G11C8/10 , H03M13/11 , G11C29/44 , G11C16/04
Abstract: Methods, systems, and media for decoding data are described. A sequence of read-level voltages for decoding operations may be determined based on a trend of decoding success indicators, including a first decoding success indicator and a second decoding success indicator. The first decoding success indicator is obtained from a more recent successful decoding operation. The first one of the sequence may be set to a read-level voltage of the first decoding success indicator. If the read-level voltage of the first decoding success indicator is less than a read-level voltage of the second decoding success indicator, then the trend is decreasing, and the second one of the sequence may be set to a read-level voltage less than that of the first one of the sequence. After executing one or more decoding operations, the decoding success indicators may be updated based on the read-level voltage of the current successful decoding operation.
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公开(公告)号：US10180794B2
公开(公告)日：2019-01-15
申请号：US15426951
申请日：2017-02-07
Applicant: Western Digital Technologies, Inc.
Inventor： Niang-Chu Chen , Jun Tao
Abstract: The subject technology provides reduced overhead in Low Density Parity Check decoding operations. A method includes receiving a hard decode fail indication from a decoder that decoding first raw data read from non-volatile memory in response to a first read command using a first set of voltages failed. The method includes determining a count of available soft decoders of a plurality of soft decoders of the decoder. The method includes determining, based on the count of available soft decoders and a pending number of soft decoding requests, a number of soft decoding requests to issue. The method includes issuing the determined number of soft decoding requests to respective ones of the available soft decoders for soft decoding the first raw data in parallel. The method includes receiving from the decoder a success indication of successful decoding.
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公开(公告)号：US10083754B1
公开(公告)日：2018-09-25
申请号：US15614415
申请日：2017-06-05
Applicant: Western Digital Technologies, Inc.
Inventor： Niang-Chu Chen , Scott Kayser , Jun Tao
CPC classification number: G11C7/22 , G06F11/1012 , G06F13/16 , G11C7/1006 , G11C11/5642 , G11C16/26
Abstract: Multiple reads of memory cells of a flash memory device are initiated at different read levels to obtain raw data. For each different read level, multiple decoding operations are initiated to decode the raw data, each decoding operation using a different one of a plurality of sets of decoding information associated with the different read level. Decoding success rates are determined for one or more of the plurality of sets based on the one or more of the plurality of sets being used to successfully decode data and, for each different read level, an order of the plurality of sets is determined based on the determined success rates. A selected set of decoding information is selected for use in decoding raw data obtained from a read performed at a respective read level based on the respective read level and the set order of the plurality of sets for the respective read level.
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公开(公告)号：US10747454B1
公开(公告)日：2020-08-18
申请号：US16259828
申请日：2019-01-28
Applicant: Western Digital Technologies, Inc.
Inventor： Niang-Chu Chen , Jun Tao
Abstract: Apparatus, media, methods, and systems for data storage systems and methods for self-adaptive chip-enable setup time. A data storage system may comprise one or more non-volatile memory device and a controller. The controller is configured to determine whether a command to a first non-volatile memory device of the one or more non-volatile memory devices is dropped. The controller is configured to, when the command to the first non-volatile memory device is determined to be dropped, update a first counter value indicating a number of commands to the first non-volatile memory device that are dropped. The controller is configured to, when the command to the first non-volatile memory device is determined to be dropped, increase a value of a chip-enable setup time parameter for the first non-volatile memory device by a first time duration, based on at least one of the first counter value and one or more parameter values of the first non-volatile memory device.
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Patent Agency Ranking
公开(公告)号：US11093326B2
公开(公告)日：2021-08-17
申请号：US16751126
申请日：2020-01-23
Applicant: Western Digital Technologies, Inc.
Inventor： Jun Tao , Niang-Chu Chen , Mark Joseph Dancho , Xiaoheng Chen
Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.
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公开(公告)号：US11086529B2
公开(公告)日：2021-08-10
申请号：US16143242
申请日：2018-09-26
Applicant: Western Digital Technologies, Inc.
Inventor： Jun Tao , Niang-Chu Chen
Abstract: Apparatus, media, methods, and systems are disclosed for improved data relocation based on read-level voltages. A data storage system may include a non-volatile memory device including a source region and a destination region. The destination region may include a first destination block and a second destination block. A controller may read first data in the source region using a first read-level voltage, and read second data in the source region using a second read-level voltage. The controller may associate, based on the first and second read-level voltages, each of the first data and the second data with a respective one of the first and the second destination blocks. The controller may cause each of the first and second data to be stored in the associated one of the first and second destination blocks.
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公开(公告)号：US11301369B2
公开(公告)日：2022-04-12
申请号：US16256994
申请日：2019-01-24
Applicant: Western Digital Technologies, Inc.
Inventor： Amir Hossein Gholamipour , Mark David Myran , Chandan Mishra , Namhoon Yoo , Jun Tao
IPC: G06F12/00 , G06F11/00 , G06F12/02 , G06F11/14 , G06F12/0804
Abstract: Disclosed are systems and methods for providing logical to physical (L2P) table management using low-latency NVM to reduce solid state drive (SSD) random access memory (RAM) footprint. A method includes determining a logical to physical (L2P) mapping of a logical address to a physical address in a flash storage, for an operation directed to the logical address. The method also includes adding a data entry, comprising the L2P mapping, to an open journal structure in RAM. The method also includes adding a log entry, comprising the L2P mapping, to a buffer in the RAM. The method also includes flushing the buffer to a low-latency NVM storage in response to determining that the buffer has satisfied a size threshold. Reads, snapshotting and L2P table recovery are also described.
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公开(公告)号：US11211949B2
公开(公告)日：2021-12-28
申请号：US16824519
申请日：2020-03-19
Applicant: Western Digital Technologies, Inc.
Inventor： Jun Tao , Niang-Chu Chen
Abstract: Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.
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公开(公告)号：US11017867B2
公开(公告)日：2021-05-25
申请号：US16824584
申请日：2020-03-19
Applicant: Western Digital Technologies, Inc.
Inventor： Niang-Chu Chen , Jun Tao
IPC: G11C16/26 , G11C16/08 , G11C11/56 , G11C11/408 , G11C29/42 , G11C29/52 , G11C8/10 , H03M13/11 , G11C29/44 , G11C16/04
Abstract: Methods, systems, and media for decoding data are described. A sequence of read-level voltages for decoding operations may be determined based on a trend of decoding success indicators, including a first decoding success indicator and a second decoding success indicator. The first decoding success indicator is obtained from a more recent successful decoding operation. The first one of the sequence may be set to a read-level voltage of the first decoding success indicator. If the read-level voltage of the first decoding success indicator is less than a read-level voltage of the second decoding success indicator, then the trend is decreasing, and the second one of the sequence may be set to a read-level voltage less than that of the first one of the sequence. After executing one or more decoding operations, the decoding success indicators may be updated based on the read-level voltage of the current successful decoding operation.
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