公开(公告)号：US11789860B2

公开(公告)日：2023-10-17

申请号：US17694470

申请日：2022-03-14

Applicant: Western Digital Technologies, Inc.

Inventor： Amir Hossein Gholamipour ,  Mark David Myran ,  Chandan Mishra ,  Namhoon Yoo ,  Jun Tao

IPC: G06F11/00 ,  G06F12/00 ,  G06F12/02 ,  G06F11/14 ,  G06F12/0804

CPC classification number: G06F12/0246 ,  G06F11/1441 ,  G06F11/1471 ,  G06F12/0804 ,  G06F2201/81 ,  G06F2201/84 ,  G06F2212/1024 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: Disclosed are systems and methods for providing logical to physical (L2P) table management using low-latency NVM to reduce solid state drive (SSD) random access memory (RAM) footprint. A method includes determining a logical to physical (L2P) mapping of a logical address to a physical address in a flash storage, for an operation directed to the logical address. The method also includes adding a data entry, comprising the L2P mapping, to an open journal structure in RAM. The method also includes adding a log entry, comprising the L2P mapping, to a buffer in the RAM. The method also includes flushing the buffer to a low-latency NVM storage in response to determining that the buffer has satisfied a size threshold. Reads, snapshotting and L2P table recovery are also described.

公开(公告)号：US20190339904A1

公开(公告)日：2019-11-07

申请号：US15971869

申请日：2018-05-04

Applicant: Western Digital Technologies, Inc.

Inventor： Mark David Myran ,  Chandan Mishra ,  Amir Hossein Gholamipour ,  Aldo Giovanni Cometti ,  Namhoon Yoo

IPC: G06F3/06 ,  G06F12/1009

Abstract: Aspects of the present disclosure provide systems and methods for operating a solid state drive (SSD) using two-level indirection architecture. The SSD receives a command to perform a data operation in a NAND array and a logical address for the data operation. The SSD then converts the logical address to a physical address using a two-stage logical-to-physical (L2P) mapping table that includes a first stage stored in a byte-rewritable memory and a second stage stored in a block-erasable non-volatile memory (NVM). The SSD performs the data operation in the NAND array based on the physical address. The byte-rewritable memory may any byte-rewritable persistent memory. The block-erasable low latency NVM may be a flash memory that has lower latency than NAND array.

公开(公告)号：US11301369B2

公开(公告)日：2022-04-12

申请号：US16256994

申请日：2019-01-24

Applicant: Western Digital Technologies, Inc.

Inventor： Amir Hossein Gholamipour ,  Mark David Myran ,  Chandan Mishra ,  Namhoon Yoo ,  Jun Tao

IPC: G06F12/00 ,  G06F11/00 ,  G06F12/02 ,  G06F11/14 ,  G06F12/0804

Abstract: Disclosed are systems and methods for providing logical to physical (L2P) table management using low-latency NVM to reduce solid state drive (SSD) random access memory (RAM) footprint. A method includes determining a logical to physical (L2P) mapping of a logical address to a physical address in a flash storage, for an operation directed to the logical address. The method also includes adding a data entry, comprising the L2P mapping, to an open journal structure in RAM. The method also includes adding a log entry, comprising the L2P mapping, to a buffer in the RAM. The method also includes flushing the buffer to a low-latency NVM storage in response to determining that the buffer has satisfied a size threshold. Reads, snapshotting and L2P table recovery are also described.