公开(公告)号：US20220181339A1

公开(公告)日：2022-06-09

申请号：US17545519

申请日：2021-12-08

Applicant: Winbond Electronics Corp.

Inventor： Chien-Hsien WU ,  Chun-Hung LIN ,  Kao-Tsair TSAI ,  Yao-Ting TSAI

IPC: H01L27/11517 ,  H01L29/66

Abstract: A method for manufacturing a non-volatile memory device is provided. The method includes forming a trench through a sacrificial layer and extending into a substrate, filling a first insulating material into the trench, and implanting a dopant in the first insulating material by an implantation process. Then, the first insulating material is partially removed to form a first recess between the sacrificial layers. The lowest point of the first recess is lower than the top surface of the substrate. The method includes filling a second insulating material in the first recess and removing the sacrificial layer to form a second recess adjacent to the second insulating material The method includes forming a first polycrystalline silicon layer in the second recess, and sequentially forming a dielectric layer and a second polycrystalline silicon layer on the first polycrystalline silicon layer.

公开(公告)号：US20190305110A1

公开(公告)日：2019-10-03

申请号：US16374162

申请日：2019-04-03

Applicant: Winbond Electronics Corp.

Inventor： Sih-Han CHEN ,  Chien-Ting CHEN ,  Yao-Ting TSAI ,  Hsiu-Han LIAO

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/285

Abstract: A method for forming a self-aligned contact includes providing a substrate with a plurality of gate structures formed on the substrate. The method also includes forming a spacer liner on the gate structures and the substrate. The method also includes forming a sacrificial layer between the gate structures and on the gate structures. The method also includes forming a plurality of dielectric plugs through the sacrificial layer above the gate structures. The method also includes removing the sacrificial layer to form a plurality of contact openings between the gate structures. The method also includes forming an etch resistant layer conformally covering the sidewall and the bottom of the contact openings. The method also includes forming a plurality of contact plugs in the contact openings.

公开(公告)号：US20250079315A1

公开(公告)日：2025-03-06

申请号：US18677434

申请日：2024-05-29

Applicant: Winbond Electronics Corp.

Inventor： Jian-Ting CHEN ,  Yao-Ting TSAI ,  Bo-Lun WU ,  Sih-Han CHEN

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528

Abstract: The method for forming the semiconductor structure includes the following steps. A substrate that is divided into a cell region and a peripheral region is provided. A bottom dielectric layer is formed on the substrate. A first stacked structure and a second stacked structure are formed on the bottom dielectric layer. The first stacked structure is disposed in the cell region and the second stacked structure is disposed in the peripheral region. The first stacked structure is patterned to form first conductive stacks. A first cleaning process is performed. A first repair dielectric layer is formed on the first conductive stacks, the second stacked structure, and the bottom dielectric layer. The second stacked structure is patterned to form second conductive stacks. A second cleaning process is performed. A second repair dielectric layer is formed on the first conductive stacks, the second conductive stacks, and the bottom dielectric layer.

公开(公告)号：US20190221487A1

公开(公告)日：2019-07-18

申请号：US16171028

申请日：2018-10-25

Applicant: Winbond Electronics Corp.

Inventor： Lun-Lun CHEN ,  Hsiu-Han LIAO ,  Yao-Ting TSAI

IPC: H01L21/66 ,  H01L23/58 ,  H01L23/522 ,  H01L23/31 ,  H01L23/528 ,  H01L23/29

Abstract: A semiconductor device having a conductive pad is provided, wherein the conductive pad includes a substrate, a dielectric layer, a plurality of vias, and a patterned conductive pad. The dielectric layer is overlying the substrate. The vias are disposed in the dielectric layer. The patterned conductive pad is disposed over the dielectric layer. The conductive pad includes, from a top view, at least three first conductive strips spaced apart from each other, arranged in different rows. The conductive strips in different rows are electrically and physically connected by a plurality of conductive strings. The conductive strings between different rows of the conductive strips are arranged in a staggered manner. The vias are disposed under the conductive strips.

公开(公告)号：US20250081542A1

公开(公告)日：2025-03-06

申请号：US18673901

申请日：2024-05-24

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting TSAI ,  Po-Yen HSU

IPC: H01L29/423 ,  H01L21/762 ,  H01L21/768 ,  H01L29/66

Abstract: A method for forming a semiconductor structure is provided. The method includes providing a semiconductor substrate with a tunnel dielectric layer, a conductive layer and a hard mask layer; etching the semiconductor layer, the tunnel dielectric layer, the conductive layer and the hard mask layer to define stack structures and trenches; forming a liner on the sidewalls of the stack structures; forming an isolation structure in the trenches; removing the hard mask layer to form openings exposing the conductive layer; filling the openings with a conductive material to form a floating gate which includes a lower portion covered by the liner and an upper portion not covered by the liner; recessing the isolation structure to expose the sidewalls of the upper portion of the floating gate; forming an inter-gate dielectric (IGD) layer on the isolation structure and the floating gate; and forming a control gate on the IGD layer.

公开(公告)号：US20240304681A1

公开(公告)日：2024-09-12

申请号：US18346507

申请日：2023-07-03

Applicant: Winbond Electronics Corp.

Inventor： Chi-Ching LIU ,  Chia-Ming LIU ,  Yao-Ting TSAI ,  Chang-Tsung PAI

IPC: H01L21/28 ,  H01L21/762 ,  H01L29/423 ,  H10B41/30

CPC classification number: H01L29/40114 ,  H01L21/76224 ,  H01L29/42336 ,  H10B41/30

Abstract: The method of forming the semiconductor device includes the following steps. An isolation structure is formed between a plurality of active areas. Semiconductor structures are formed over the active areas, and a portion of each semiconductor structure is embedded in the isolation structure. Sacrificial structures are formed on the semiconductor structures. An ion implantation process is performed to form implanted regions between the portions of the semiconductor structures embedded in the isolation structure. The sacrificial structures are removed to form patterned semiconductor structures. A dielectric structure is formed on the patterned semiconductor structure. A control structure is formed on the dielectric structure.

公开(公告)号：US20220189975A1

公开(公告)日：2022-06-16

申请号：US17685786

申请日：2022-03-03

Applicant: Winbond Electronics Corp.

Inventor： Chih-Jung NI ,  Chuan-Chi CHOU ,  Yao-Ting TSAI

IPC: H01L27/11521 ,  H01L27/11526 ,  G11C5/06

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure disposed on the substrate, an inter-gate dielectric layer disposed on the floating gate structure, and a control gate structure disposed on the inter-gate dielectric layer. The control gate structure includes an electrode layer disposed on the inter-gate dielectric layer, a contact layer disposed on the electrode layer, and a cap layer disposed on the contact layer. The first spacer is disposed on a sidewall of the control gate structure and covering the electrode, the contact layer and the cap layer. A bottom surface of the first spacer is positioned between a bottom surface and a top surface of the electrode layer.

公开(公告)号：US20200152647A1

公开(公告)日：2020-05-14

申请号：US16555736

申请日：2019-08-29

Applicant: Winbond Electronics Corp.

Inventor： Chih-Jung NI ,  Chuan-Chi CHOU ,  Yao-Ting TSAI

IPC: H01L27/11521 ,  G11C5/06 ,  H01L27/11526

Abstract: The present invention includes a semiconductor structure having a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure, an inter-gate dielectric layer, and a control gate structure. The floating gate structure is disposed on the substrate. The inter-gate dielectric layer is disposed on the floating gate structure. The control gate structure is deposited on the inter-gate dielectric layer and includes an electrode layer, a contact layer and a cap layer. The electrode layer is disposed on the inter-gate dielectric layer. The contact layer is disposed on the electrode layer. The cap layer is disposed on the contact layer. The first spacer is disposed on sidewalls of the control gate structure and covers the electrode layer, the contact layer, and the cap layer. Furthermore, the bottom surface of the first spacer is disposed between the bottom surface and the top surface of the electrode layer.

公开(公告)号：US20200035794A1

公开(公告)日：2020-01-30

申请号：US16521311

申请日：2019-07-24

Applicant: Winbond Electronics Corp.

Inventor： Jian-Ting CHEN ,  Yao-Ting TSAI ,  Jung-Ho CHANG ,  Hsiu-Han LIAO

IPC: H01L21/28 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/423 ,  H01L29/49 ,  H01L21/3215 ,  H01L21/311 ,  H01L29/788 ,  H01L29/66

Abstract: A non-volatile memory device and its manufacturing method are provided. The method includes the following steps. A plurality of isolation structures are formed in a substrate. A first polycrystalline silicon layer is formed in the substrate and between two adjacent isolation structures. A first implantation process is performed to implant a first dopant into the first polycrystalline silicon layer and the isolation structures. A portion of each of the isolation structures is partially removed, and the remaining portion of each of the isolation structures has a substantially flat top surface. An annealing process is performed after partially removing the isolation structures to uniformly diffuse the first dopant in the first polycrystalline silicon layer. A dielectric layer is formed on the first polycrystalline silicon layer, and a second polycrystalline silicon layer is formed on the dielectric layer.