公开(公告)号：US12027207B2

公开(公告)日：2024-07-02

申请号：US17646549

申请日：2021-12-30

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： DongXue Zhao ,  Tao Yang ,  Yuancheng Yang ,  Lei Liu ,  Di Wang ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  ZongLiang Huo

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: This disclosure is directed to methods for performing operations on a memory device. The memory device can include a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar and a bit line formed above the drain cap. The method can include applying a first positive voltage bias to the bottom select gate and applying a second positive voltage bias to the word line. The method can also include applying a third positive voltage bias to the bit line after the word line reaches the second positive voltage bias. The method can further include applying a ground voltage to the word line and applying the ground voltage to the bit line.

公开(公告)号：US20230189516A1

公开(公告)日：2023-06-15

申请号：US17648783

申请日：2022-01-24

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Tao Yang ,  DongXue Zhao ,  Yuancheng Yang ,  Lei Liu ,  Kun Zhang ,  Di Wang ,  Wenxi Zhou ,  ZhiLiang Xia ,  ZongLiang Huo

IPC: H01L27/11556 ,  G11C5/02 ,  H01L27/11582 ,  H01L23/532

CPC classification number: H01L27/11556 ,  G11C5/025 ,  H01L27/11582 ,  H01L23/53204

Abstract: The present disclosure is directed to a memory structure including a staircase structure. The staircase structure can include a bottom select gate, a plate line formed above the bottom select gate, and a word line formed above the plate line. The pillar can extend through the bottom select gate, the plate line, and the word line. The memory structure can also include a source structure formed under the pillar and a drain cap formed above the pillar. The memory structure can further include a bit line formed above the drain cap.

公开(公告)号：US20240407174A1

公开(公告)日：2024-12-05

申请号：US18474872

申请日：2023-09-26

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Tao Yang ,  DongXue Zhao ,  Changzhi Sun ,  Wenxi Zhou ,  ZhiLiang Xia ,  ZongLiang Huo

IPC: H10B53/20 ,  G11C5/06 ,  G11C11/22 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10 ,  H10B51/20 ,  H10B53/10

Abstract: The present application provides a semiconductor device and a fabrication method thereof, and a memory system. The semiconductor structure includes a first semiconductor structure which includes: a first select transistor including a first channel layer; a second select transistor including a gate; and a capacitor structure including a first electrode layer, wherein two ends of the first electrode layer are connected with the gate of the second select transistor and the first channel layer of the first select transistor respectively. The present application can avoid the problem of state destruction caused by reading operation.

公开(公告)号：US20230282576A1

公开(公告)日：2023-09-07

申请号：US17736725

申请日：2022-05-04

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Yuancheng Yang ,  DongXue Zhao ,  Tao Yang ,  Lei Liu ,  Di Wang ,  Kun Zhang ,  Wenxi Zhou ,  ZhiLiang Xia ,  ZongLiang Huo

IPC: H01L23/528 ,  H01L27/11551 ,  H01L27/11578

CPC classification number: H01L23/5283 ,  H01L27/11551 ,  H01L27/11578

Abstract: Embodiments of three-dimensional memory devices are disclosed. A disclosed memory structure can comprises a memory cell, a bit line contact coupled to the memory cell, a bit line coupled to the bit line contact, a source line contact coupled to the memory cell, and a source line coupled to the source line contact. The memory cell comprises a cylindrical body having a cylindrical shape, an insulating layer surrounding the cylindrical body, a word line contact surrounding a first portion of the insulating layer, the word line contact coupled to a word line, and a plurality of plate line contact segments surrounding a second portion of the insulating layer, the plurality of plate line contact segments coupled to a common plate line.