公开(公告)号：JP2004007693A

公开(公告)日：2004-01-08

申请号：JP2003146733

申请日：2003-05-23

Applicant: ST MICROELECTRONICS INC

Inventor： GRAUMANN PETER J

IPC: H03M13/41 ,  H04B3/06 ,  H04L1/00

Abstract: PROBLEM TO BE SOLVED: To provide a technology for enhancing the gain performance of a Viterbi decoder. SOLUTION: The system and method of this invention stores data related to a best path and a secondary path in a Viterbi decoder, uses the stored data to decide the slicer error of a present symbol with respect to the best path and the secondary path, and corrects an error with respect to the preceding symbol in response to the decided slicer error. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004007636A

公开(公告)日：2004-01-08

申请号：JP2003126433

申请日：2003-05-01

Applicant: ST MICROELECTRONICS INC

Inventor： CERVINI STEFANO

IPC: H04B7/26 ,  H04B1/707

Abstract: PROBLEM TO BE SOLVED: To provide a demodulator with reduced delay and power consumption. SOLUTION: A demodulator in a wireless communication network for coupling symbols without need to store received symbols in a buffer for later search and accumulation is provided. The demodulator has more than one accumulators which can accumulate received symbols. Each of the received symbols is associated with a physical channel and a transmission route. The demodulator has a multiplexer to route the received symbols from multiple accumulators to an appropriate accumulator selected. Each of the symbols received from different transmission routes is routed to and accumulated in an appropriate accumulator based on a value of an indicator associated with the physical channel of the received symbol and the transmission route of the received symbol. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003208304A

公开(公告)日：2003-07-25

申请号：JP2002377352

申请日：2002-12-26

Applicant: ST MICROELECTRONICS INC

Inventor： CHREN WILLIAM A JR

IPC: G06F7/00 ,  G06F7/72 ,  H03M7/18

Abstract: PROBLEM TO BE SOLVED: To provide an improved arithmetic circuit to be used with a residue number system (RNS). SOLUTION: A self-synchronized data processing circuit module is provided. Data are provided to the data processing circuit along with a request handshaking input. The data processing circuit has an isochronous processing delay for all data inputs. An example of a data processing circuit with isochronous processing delay is an OHRNS (one hot residue number system) arithmetic processing circuit. The data processing circuit processes the input data while the request input propagates through a delay circuit that has substantially the same processing delay as the data processing circuit. Thus, the propagation delay of the request signal is substantially equal to the data processing circuit's processing time. This allows the output of the delay circuit to be used to both latch the output of the data processing circuit and provide a 'data ready' output. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003202981A

公开(公告)日：2003-07-18

申请号：JP2002354116

申请日：2002-12-05

Applicant: ST MICROELECTRONICS INC

Inventor： HUANG LUN BIN

IPC: G06F7/02 ,  G06F9/34 ,  G06F12/08

Abstract: PROBLEM TO BE SOLVED: To provide an address range checking circuit that does not require a large comparator circuit. SOLUTION: This address range checking circuit is capable of determining if a target address A (M: 0) is within an address space having 2N address locations beginning at a base address location B (M: 0). The address range checking circuit does not require a large comparator circuit, and accordingly, can quickly operate in comparison with the conventional technology. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003188166A

公开(公告)日：2003-07-04

申请号：JP2002348626

申请日：2002-11-29

Applicant: ST MICROELECTRONICS INC

Inventor： SIEGEL HARRY M ,  LANE FRED P

IPC: H01L23/29 ,  A61B5/103 ,  G06K9/00 ,  H01L21/312 ,  H01L23/31

Abstract: PROBLEM TO BE SOLVED: To enhance durability of a physical interface exposed to the environment of a semiconductor device, e.g. an integrated circuit. SOLUTION: In a touch sensitive semiconductor chip having a physical interface exposed to the environment, the surface of the physical interface is coated with fluorocarbon polymer. The polymer has a high scratch durability and a low permittivity exhibiting a low attenuation for the electric field. The polymer can be employed in place of conventional passivation so that a thin layer of low permittivity can be provided between an object touching the physical interface and a capacitive detection circuit existing beneath the polymer. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003179880A

公开(公告)日：2003-06-27

申请号：JP2002253919

申请日：2002-08-30

Applicant: ST MICROELECTRONICS INC

Inventor： HADDAD SEMIR S

IPC: H04N5/93 ,  G11B20/10 ,  G11B20/12 ,  H04N5/04 ,  H04N5/44 ,  H04N5/76 ,  H04N5/781 ,  H04N5/92 ,  H04N7/173 ,  H04N7/26 ,  H04N7/50 ,  H04N9/804 ,  H04N19/00 ,  H04N21/4147 ,  H04N21/43 ,  H04N21/434 ,  H04N21/4385 ,  H04N21/845 ,  H04N7/24

Abstract: PROBLEM TO BE SOLVED: To provide a technique of a digital video recorder (DVR) for detecting the start code in an MPEG video stream. SOLUTION: The MPEG decoder has a controller that to detects the start codes in a received bit-stream, and each of such codes has a three-byte start code prefix and a one-byte start code value. The controller is operable to fetch a thirty-two bit word of the received bit-stream, determines whether or not the start code prefix and the start code value are properly aligned within the thirty-two bit word, and determine whether or not the least significant byte of the thirty-two bit word may be part of the start code prefix if not properly aligned within the thirty-two bit word. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003158724A

公开(公告)日：2003-05-30

申请号：JP2002252997

申请日：2002-08-30

Applicant: ST MICROELECTRONICS INC

Inventor： HADDAD SEMIR S

IPC: G11B20/10 ,  G11B27/00 ,  G11B27/30 ,  H04N5/76 ,  H04N5/783 ,  H04N5/85 ,  H04N5/91 ,  H04N5/92 ,  H04N5/93 ,  H04N9/804 ,  H04N9/806

Abstract: PROBLEM TO BE SOLVED: To provide a video indexing system and a method optimized to perform a special mode reproducing operation in a digital video recorder. SOLUTION: The system and method for realizing a special mode reproducing operation in a digital video recorder comprises an intraframe index unit capable of receiving an incoming MPEG video stream and identifying a data packet related to an intraframe. The intraframe index unit corrects the header information in a first data packet related to a first intraframe in order to include positional information for identifying the storage address of a second data packet related to a second intraframe.

公开(公告)号：JP2003140636A

公开(公告)日：2003-05-16

申请号：JP2002224315

申请日：2002-08-01

Applicant: ST MICROELECTRONICS INC

Inventor： COLAVIN OSVALDO M

IPC: G06F3/14 ,  G06F12/02 ,  G09G3/36 ,  G09G5/00 ,  G09G5/34 ,  G09G5/36

Abstract: PROBLEM TO BE SOLVED: To provide an improved system and method which buffer and access image data. SOLUTION: Provided are a method and apparatus for buffering 2-dimensional graphical image data to be supplied to a scrolling display controller. A 2-dimensional, circularly addressed data buffer is used to store a portion of an entire image. The data buffer is larger than the amount of data displayed at one time. A user enters scrolling commands and the display scrolls around the data initially in the buffer. new data is loaded into the buffer as the displayed data approaches the edge of the buffered data.

公开(公告)号：JP2003114795A

公开(公告)日：2003-04-18

申请号：JP2002261802

申请日：2002-09-06

Applicant: ST MICROELECTRONICS INC

Inventor： HOSSAIN RAZAK ,  HUANG LUN-BIN

IPC: G06F9/38 ,  G06F7/00 ,  G06F7/02 ,  G06F7/50 ,  G06F7/505 ,  G06F9/32

Abstract: PROBLEM TO BE SOLVED: To provide technique for improving processing speed of comparison following addition in a computation system. SOLUTION: This computation system comprises plural full adders, and each of them receives reversal for each bit of single bits in third data, single bits in second data, and single bits in first data, and supplies a total output and a carry output. An exclusive OR logic module receives the total output of the first one of the full adders and the carry output of the second one of the full adders, and supplies an exclusive OR output. An AND logic module has plural inputs and an AND output. The exclusive OR output is electrically connected to one of the plural inputs of the AND logic module. The AND output supplies a signal representing if the first data are equal to the total of the second data and the third data.

公开(公告)号：JP2003109392A

公开(公告)日：2003-04-11

申请号：JP2002226102

申请日：2002-08-02

Applicant: ST MICROELECTRONICS INC

Inventor： MICHAEL ORON ,  SEVER ILAN

IPC: G11C16/06 ,  G05F3/26 ,  G11C5/14 ,  G11C7/14 ,  G11C16/28

Abstract: PROBLEM TO BE SOLVED: To provide a technology for generating effectively a reference current in a nonvolatile semiconductor memory. SOLUTION: A reference current generator circuit supplies reference current to a sense amplifier in a flash memory device. This circuit has a reference current generator generating a reference current used for a sense amplifier circuit. A current buffer circuit in the flash memory device mirrors the reference current, and a plurality of mirrored reference currents is applied to the reference input. A startup circuit is utilized in order to provide a fast setting time of the reference node appearing at the input of the sense amplifier.