公开(公告)号：DE3376940D1

公开(公告)日：1988-07-07

申请号：DE3376940

申请日：1983-02-01

Applicant: IBM

Inventor： VENESKI GERARD ANTHONY ,  THOMA NANDOR GYORGY ,  CASES MOISES

IPC: H03K19/177 ,  G06F9/22 ,  H03K5/15 ,  G06F9/28

Abstract: A clocking mechanism is provided for multiple overlapped dynamic programmable logic arrays which are used in a digital control unit wherein a sequence of control words are used to produce successive groups of control point signals. Such a control unit includes a plurality of dynamic programmable logic arrays (24-29) for individually producing different ones of the control words. Each such control word includes a strobe field which is coded to identify a programmable logic array other than the one which produced it. The control unit also includes control circuitry (30, 31, 35, 37, 43, 45) responsive to the control words for producing the control point signals for successive machine control cycles. The control circuitry includes circuitry (37, 45) responsive to the strobe field in each control word for producing a strobe signal (Sl, S2, SA, SB, SC or SD) for selecting the next programmable logic array (24-29) to supply a control word to the control circuitry. This control unit further includes clocking circuitry (60) responsive to the strobe signals (S1, S2, SA, etc.) produced by the control circuitry for producing clocking signals (PC1-PC9) for the dynamic programmable logic arrays (24-29). Such clocking circuitry includes only combinatorial logic circuitry for producing the clocking signals.

公开(公告)号：GB2490561B

公开(公告)日：2013-11-13

申请号：GB201201084

申请日：2010-10-29

Applicant: IBM

Inventor： MUTNURY BHYRAV MURTHY ,  CASES MOISES ,  NA NANJU

IPC: H05K1/02 ,  H01L23/64 ,  H05K1/16

Abstract: Improving signal quality in a high-frequency chip package by resistively connecting an open-ended plating stub to ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A conductive first layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A resistor is used to resistively couple the plating stub to a ground layer.

公开(公告)号：AT492886T

公开(公告)日：2011-01-15

申请号：AT08775264

申请日：2008-07-21

Applicant: IBM

Inventor： CASES MOISES ,  PHAM NAM ,  ARAUJO DANIEL ,  MUTNURY BHYRAV ,  DREPS DANIEL

IPC: G11C29/56 ,  G06F11/273

Abstract: A programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module. The memory module may emulate multiple selectable memory module types, and may include a complete storage array to provide standard memory module operation.

公开(公告)号：CA2669618A1

公开(公告)日：2010-03-25

申请号：CA2669618

申请日：2009-06-18

Applicant: IBM

Inventor： MUTNURY BHYRAV MURTHY ,  CASES MOISES ,  NA NANJU ,  KIM TAE HONG

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H05K1/14

Abstract: Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.

公开(公告)号：DE112010004649B4

公开(公告)日：2017-07-27

申请号：DE112010004649

申请日：2010-10-29

Applicant: IBM

Inventor： MUTNURY BHYRAV MURTHY ,  CASES MOISES ,  NA NANJU

IPC: H01L23/498 ,  H05K1/02

Abstract: Mehrschichtiges Substrat (40) zum Verbinden eines Chips (22) mit einer Leiterplatte (10), welches das Folgende umfasst: – ein Substrat (40), welches eine erste Seite (23) mit einer zentralen Befestigungsstelle (42) zum Aufnehmen des Chips aufweist; – ein elektrisch leitfähiges Material, welches auf der ersten Seite (23) des Substrats (40) angeordnet ist, wobei das elektrisch leitfähige Material eine Signalzwischenverbindung (46) in einem Abstand von der Chipbefestigungsstelle, eine Signalleiterbahn (44), die sich bis zu der Signalzwischenverbindung erstreckt, und eine Plattierungsstichleitung (48) bildet, die sich von der Signalzwischenverbindung in Richtung eines Randes (49) des Substrats erstreckt; – eine elektrisch leitfähige Massefläche, welche parallel zu der ersten Seite (23) verläuft und durch eine elektrisch nicht leitende Schicht von der ersten Seite getrennt ist; und – einen Widerstand (50), welcher die Plattierungsstichleitung (48) mit der Massefläche verbindet, – wobei der Widerstand (50) einen diskreten Widerstand umfasst, der an der ersten Seite (23) des Substrats befestigt ist, wobei der diskrete Widerstand eine erste Leitung umfasst, die mit der Plattierungsstichleitung (48) elektrisch verbunden ist, und eine zweite Leitung umfasst, die mit einer Massedurchkontaktierung (46B) elektrisch verbunden ist, wobei die Massedurchkontaktierung (46B) mit der Massefläche elektrisch verbunden ist.

公开(公告)号：GB2490561A

公开(公告)日：2012-11-07

申请号：GB201201084

申请日：2010-10-29

Applicant: IBM

Inventor： MUTNURY BHYRAV MURTHY ,  CASES MOISES ,  NA NANJU

IPC: H05K1/02 ,  H01L23/64 ,  H05K1/16

Abstract: Improving signal quality in a high-frequency chip package by resistively connecting an open-ended plating stub to ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A conductive first layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A resistor is used to resistively couple the plating stub to a ground layer.

公开(公告)号：MY115559A

公开(公告)日：2003-07-31

申请号：MYPI9704867

申请日：1997-10-16

Applicant: IBM

Inventor： CASES MOISES ,  WU LEON L

IPC: H01H83/20 ,  H01L27/02

Abstract: A DECOUPLING CAPACITOR (102) FOR AN INTEGRATED CIRCUIT IS OPERATIVELY COUPLED TO A SUPPLY (101) AND TO CONTROL CIRCUITRY FOR ISOLATING THE CAPACITOR. THE CONTROL CIRCUITRY AUTOMATICALLY ISOLATES THE CAPACITOR IN RESPONSE TO A CURRENT THROUGH THE CAPACITOR EXCEEDING A CERTAIN THRESHOLD, BUT TENDS TO RESTORE THE CAPACITOR TO OPERATION IF THE CURRENT IS MERELY CAUSED BY MOMENTARY CONDITIONS, RATHER THAN SUBSTANTIAL FAILURE OF THE CAPACITOR. THE CONTROL CIRCUITRY INCLUDES A FIRST CONTROL DEVICE (108) FOR AUTOMATICALLY SWITCHING TO AN OFF STATE TO ISOLATE THE CAPACITOR IN RESPONSE TO A VOLTAGE PRODUCED BY THE CURRENT EXCEEDING A CERTAIN THRESHOLD. A DISCHARGING DEVICE TENDS TO DISCHARGE THE VOLTAGE AND AUTOMATICALLY TURN ON THE FIRST DEVICE WHEN THE CURRENT IS CAUSED BY MOMENTARY CONDITIONS. THE DISCHARGING DEVICE MAY INCLUDE A CONTROL DEVICE (122) RESPONSIVE TO AN EXTERNAL CONTROL SIGNAL FOR SWITCHING THE FIRST CONTROL DEVICE ON AND OFF.

公开(公告)号：SG53109A1

公开(公告)日：1998-09-28

申请号：SG1997003781

申请日：1997-10-17

Applicant: IBM

Inventor： CASES MOISES ,  WU LEON L

IPC: H01L27/02 ,  H01L27/04

Abstract: A decoupling capacitor for an integrated circuit is operatively coupled to a supply and to control circuitry for isolating the capacitor. The control circuitry automatically isolates the capacitor in response to a current through the capacitor exceeding a certain threshold, but tends to restore the capacitor to operation if the current is merely caused by momentary conditions, rather than substantial failure of the capacitor. The control circuitry includes a first control device for automatically switching to an off state to isolate the capacitor in response to a voltage produced by the current exceeding a certain threshold. A discharging device tends to discharge the voltage and automatically turn on the first device when the current is caused by momentary conditions. The discharging device may include a control device responsive to an external control signal for switching the first control device on and off.

公开(公告)号：DE3166340D1

公开(公告)日：1984-10-31

申请号：DE3166340

申请日：1981-10-05

Applicant: IBM

Inventor： CASES MOISES ,  KRAFT WAYNE RICHARD ,  MOORE VICTOR STEWART ,  STAHL WILLIAM LEONARD JR ,  THOMA NANDOR GYORGY

IPC: H01L27/088 ,  H01L27/112 ,  H03K19/0944 ,  H03K19/177

Abstract: A logic performing cell for use in array structures is provided which allows greater density fabrication in integrated circuits and reduces operational delays. The array has a plurality of output lines intercepted by a plurality of orthogonally oriented input lines, with elements in the form of a three terminal device located at each of the intersections of the input and output lines so that logical functions are performed on interrogation signals placed on the input lines and the responses thereto placed on the output lines. The three terminal device transfer gates are connected in groups of series strings which are connected in parallel to a recombination line. These groups of series connected transfer gates comprise a programmed mix of enhancement and depletion devices. Each logic function of each group of transfer gates establishes an output which, when coupled to the recombining output circuit line, provides an overall logic function for the logic performing cell.

公开(公告)号：DE112010004649T5

公开(公告)日：2012-11-08

申请号：DE112010004649

申请日：2010-10-29

Applicant: IBM

Inventor： MUTNURY BHYRAV MURTHY ,  CASES MOISES ,  NA NANJU

IPC: H05K1/02

Abstract: Verbessern der Signalqualität in einer Hochfrequenz-Chipkapselung durch resistives Verbinden einer Plattierungsstichleitung mit offenem Ende mit Masse. In einer Ausführungsform wird ein mehrschichtiges Substrat zum Verbinden eines Chips mit einer Leiterplatte bereitgestellt. Eine leitfähige erste Schicht sorgt für eine Chipbefestigungsstelle. Eine Signalverbindung weist einen Abstand von der Chipbefestigungsstelle auf, und eine Signalspur erstreckt sich von der Nähe der Chipbefestigungsstelle bis zu der Signalverbindung. Ein Chip, der an der Chipbefestigungsstelle befestigt ist, kann durch Drahtverbindung mit der Signalspur verbunden werden. Eine Plattierungsstichleitung erstreckt sich von der Signalverbindung z. B. zu einem Rand des Substrats. Ein Widerstand wird verwendet, um die Plattierungsstichleitung mit einer Erdungsschicht resistiv zu verbinden.