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    MEMORY CONTROL METHOD AND MEMORY SYSTEM
    1.
    发明公开
    MEMORY CONTROL METHOD AND MEMORY SYSTEM 审中-公开
    存储器控制方法与存储系统

    公开(公告)号：EP1912222A4

    公开(公告)日：2009-05-13

    申请号：EP06781647

    申请日：2006-07-26

    Applicant: IBM

    Inventor： SUNAGA TOSHIO ,  FUJITA NORIO

    IPC: G11C11/401 ,  G11C11/407

    CPC classification number: G11C7/22 ,  G11C8/10 ,  G11C11/4076 ,  G11C2207/2218

    Abstract: [PROBLEMS] To shorten an access cycle time and improve data rate for data input/output (I/O), in a memory to which single-write can be performed. [MEANS FOR SOLVING PROBLEMS] The memory is provided with a latch circuit for latching a read address and a write address inputted from an address input; an address selecting circuit for selecting either the read address or the write address latched by the latch circuit as an access address; a read latch circuit for latching read data read by a memory cell array; a write latch circuit for latching write data inputted from the data input/output; and a control circuit for controlling the access address selected by the address selecting circuit by receiving a command inputted from a command input. Furthermore, the memory is provided with a control circuit for controlling timing for writing in a memory cell wherein the write data latched by the write latch circuit is activated.

    METHOD FOR MEMORY CONTROL, MEMORY CONTROL CIRCUIT WITH ECC FUNCTION AND INFORMATION PROCESSOR
    2.
    发明专利
    METHOD FOR MEMORY CONTROL, MEMORY CONTROL CIRCUIT WITH ECC FUNCTION AND INFORMATION PROCESSOR 失效

    公开(公告)号：JPH06250937A

    公开(公告)日：1994-09-09

    申请号：JP2110593

    申请日：1993-02-09

    Applicant: IBM

    Inventor： FUJITA NORIO ,  FUJITA NOBUHITO ,  YAMAZAKI SATORU ,  AIDA MITSUHIRO

    IPC: G06F11/10 ,  G06F12/16

    Abstract: PURPOSE: To suppress the increase of the number of times of memory access at the time of adding an ECC code to each data with specific length and operating an ECC processing, and to prevent the executing speed of a program from being sharply deteriorated even at the time of executing the ECC processing. CONSTITUTION: At the time of adding an ECC code to each data with specific bit length and writing the data in a memory element 20, when the length of writing data from a CPU 10 is less than the specific bit length, data previously read from the memory element 20 are held in a mean 42 different from the memory element 20, and data with the specific bit length are generated based on the held data and the writing data from the CPU 10. Thus, the ECC processing can be attained even when the reading from the memory is not necessarily operated before the writing in the memory.

    PROGRAM DISPLAYING AND SELECTING DEVICE, DIGITAL BROADCASTING RECEIVER AND SYSTEM THEREFOR
    4.
    发明专利
    PROGRAM DISPLAYING AND SELECTING DEVICE, DIGITAL BROADCASTING RECEIVER AND SYSTEM THEREFOR 失效

    公开(公告)号：JP2000224504A

    公开(公告)日：2000-08-11

    申请号：JP1989699

    申请日：1999-01-28

    Applicant: IBM

    Inventor： SAKAMOTO YOSHIFUMI ,  KUBO HIROAKI ,  FUJITA NORIO

    IPC: H04N5/445 ,  H04N5/50 ,  H04N7/025 ,  H04N7/03 ,  H04N7/035

    Abstract: PROBLEM TO BE SOLVED: To display a program table (EPG information) without disturbing the viewing of program video, to directly select a program to be viewed and to always provide an up-to-data program table for a viewer. SOLUTION: A digital broadcasting receiving system is constituted by using a digital broadcasting receiver 50 including a transmission and reception unit 58 transmitting EPG(electronic program guide) data to a program displaying and selecting device 10 and receiving a signal from the device 10, a display means (LCD) 12 displaying EPG data transmitted from the receiver 50, and the device 10 including an operation means (touch panel) 12 operating the receiver 50 and a transmission/reception unit 14 receiving EPG data transmitted from the receiver 50 and transmitting operation information inputted to the panel 12 to the receiver 50.

    APPARATUS AND METHOD FOR OVERLAY OF IMAGE
    5.
    发明专利
    APPARATUS AND METHOD FOR OVERLAY OF IMAGE 失效

    公开(公告)号：JPH09160736A

    公开(公告)日：1997-06-20

    申请号：JP30866895

    申请日：1995-11-28

    Applicant: IBM

    Inventor： YAMAZAKI SATORU ,  FUJITA NORIO

    IPC: G06F3/14 ,  G06T3/00 ,  G09G5/00 ,  G09G5/36 ,  G09G5/377 ,  G09G5/39 ,  G09G5/395

    Abstract: PROBLEM TO BE SOLVED: To provide the overlay function by hardware which solves the problem points of a conventional overlay system by addition to a general graphic controller. SOLUTION: This processing circuit has an address search circuit, an internal video memory 506, and an overlay data processing circuit 503. The address search circuit always monitors an object address at the time of the read operation of the graphic controller 502 and the internal video memory 506 stores image data to be overlaid. When a read address specified by the graphic controller 502 enters an address area to be overlaid, the image data from the internal video memory 506 are transferred to the graphic controller 502 instead of image data from an ordinary video memory.

    Memory controller and data processing system
    6.
    发明专利
    Memory controller and data processing system 未知

    公开(公告)号：SG52203A1

    公开(公告)日：1998-09-28

    申请号：SG1996000209

    申请日：1992-10-08

    Applicant: IBM

    Inventor： FUJITA NORIO ,  GOHDA MITSUHIRO

    IPC: G06F12/06

    Abstract: A memory controller 18 of a data processing system controls access to a memory having a plurality of memory banks of memory units. The banks operate in either an interleave or non-interleave access operation. The controller has map forming means 42A and 42B to map the memory units arranged in first and second predetermined orders, the second map beng in reverse order relative to the first map. Memory unit selection means 44A and 44B select which of the memory units in each of the maps an address from a cpu or a DMA controller is assigned to and control means 46 generates the physical location address in interleave or non-interleave operation in accordance with the selected unit being assigned to different banks or the same bank.

    Starting system using boot code and starting method
    7.
    发明专利
    Starting system using boot code and starting method 审中-公开
    使用引擎代码和启动方法启动系统

    公开(公告)号：JP2004334486A

    公开(公告)日：2004-11-25

    申请号：JP2003128957

    申请日：2003-05-07

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： FUJITA NORIO ,  MURAKAMI MASAHIRO

    IPC: G06F9/50 ,  G06F9/445 ,  G06F15/177

    CPC classification number: G06F9/4406

    Abstract: PROBLEM TO BE SOLVED: To omit a ROM for storing a boot code and maximize a cost reduction effect due to the ROM omission.
    SOLUTION: A starting system 10 using boot code includes an external memory 12 storing boot code, a buffer 14 connected to the external memory 12 to accumulate the boot code transferred from the external memory 12, a DMA controller 18 for commanding the transfer of the boot code from the external memory 12 to the buffer 14, and a mapping circuit 22 connected to the buffer 14 to map the boot code accumulated in the buffer 14 to a CPU 20.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：省略用于存储引导代码的ROM，并且由于ROM省略而使成本降低效果最大化。 解决方案：使用引导代码的启动系统10包括存储引导代码的外部存储器12，连接到外部存储器12的累积从外部存储器12传送的引导代码的缓冲器14，用于命令传输的DMA控制器18 从外部存储器12到缓冲器14的引导代码以及连接到缓冲器14的映射电路22，以将累积在缓冲器14中的引导代码映射到CPU 20.版权所有：（C）2005，JPO＆NCIPI

    Memory controller, chip and method for performing data transfer to display
    9.
    发明专利
    Memory controller, chip and method for performing data transfer to display 有权
    存储器控制器，芯片和执行数据传输到显示器的方法

    公开(公告)号：JP2003323146A

    公开(公告)日：2003-11-14

    申请号：JP2002123007

    申请日：2002-04-24

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： SAKAMOTO YOSHIFUMI ,  FUJITA NORIO ,  NISHINO SATOSHI

    IPC: G06F12/00 ,  G06F12/04 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00

    Abstract: PROBLEM TO BE SOLVED: To provide a memory controller, a chip and a method for performing data transfer to an LCD (liquid crystal display) so that disturbance is not generated in the display of the LCD.
    SOLUTION: A chip 10 is constituted so that a DRAM (dynamic random access memory) controller (memory controller) 14 includes a dither circuit 15 for performing dither processing in order to reduce the data amount of data at the time of performing the storing or reading of data.
    COPYRIGHT: (C)2004,JPO

    Abstract translation: 要解决的问题：提供一种存储器控制器，芯片和用于执行数据传送到LCD（液晶显示器）的方法，使得在LCD的显示器中不产生干扰。 解决方案：芯片10被构造成使得DRAM（动态随机存取存储器）控制器（存储器控制器）14包括用于执行抖动处理的抖动电路15，以便在执行抖动时减少数据的数据量 存储或读取数据。 版权所有（C）2004，JPO

    MICROPROCESSOR, SYSTEM PROVIDED WITH MICROPROCESSOR AND METHOD FOR BUS CYCLE CONTROL OF MICROPROCESSOR
    10.
    发明专利
    MICROPROCESSOR, SYSTEM PROVIDED WITH MICROPROCESSOR AND METHOD FOR BUS CYCLE CONTROL OF MICROPROCESSOR 失效

    公开(公告)号：JP2000259554A

    公开(公告)日：2000-09-22

    申请号：JP6204999

    申请日：1999-03-09

    Applicant: IBM

    Inventor： FUJITA NORIO ,  MURAKAMI MASAHIRO ,  SAKAMOTO YOSHIFUMI

    IPC: G06F13/36 ,  G06F1/04 ,  G06F9/46 ,  G06F13/362 ,  G06F13/40

    Abstract: PROBLEM TO BE SOLVED: To first execute other processing by interrupting a bus cycle under execution when another processing is requested on the condition that no READY signal is returned from the opposite party for a long time although a microprocessor issues a bus cycle. SOLUTION: This system uses a bridge chip 12 provided with a bus retry output part for outputting a bus retry (BRTY) signal and a microprocessor (MPU) 10 provided with a bus retry discriminating part for discriminating the presence/absence of the BRTY signal inputted from the bridge chip 12, a bus cycle control part for temporarily interrupting the bus cycle under execution and executing it again later when this bus retry discriminating part detects the input of the BRTY signal, an interrupt discriminating part for discriminating the presence/absence of another processing request when the bus cycle is interrupted and an interrupt control part for executing the other processing before the re-execution of the bus cycle when that interrupt discriminating part detects the other processing request.

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