公开(公告)号：DE2965742D1

公开(公告)日：1983-07-28

申请号：DE2965742

申请日：1979-09-24

Applicant: IBM

Inventor： COLLINS ROBERT WILLIAM ,  HOFFMAN ROY LOUIS ,  LOEN LARRY WAYNE ,  MITCHELL GLEN ROBERT ,  SOLTIS FRANK GERALD

IPC: G06F12/10 ,  G06F12/12 ,  G06F13/00

公开(公告)号：IT7926081D0

公开(公告)日：1979-09-28

申请号：IT2608179

申请日：1979-09-28

Applicant: IBM

Inventor： MITCHELL GLEN ROBERT ,  SOLTIS FRANK GERALD ,  HOFFMAN ROY LOUIS

IPC: G06F9/34 ,  G06F9/355 ,  G06F12/02 ,  G06F12/06 ,  G06F12/10 ,  G06F

Abstract: Virtual addressing apparatus for implementing a large virtual address in a computer system having narrow data paths, ALU, and local storage register arrays without requiring multiple passes. The virtual addressing apparatus stores the segment portion of a virtual address in a segment register and the offset portion of the virtual address in an offset register. To form a new virtual address, a new offset value is obtained by adding the displacement value given by the instruction in the instruction buffer register to the offset value stored in the offset register. The segment portion of the virtual address does not participate in the arithmetic operation for forming the new virtual address. The segment and offset portions are concatenated to form the new virtual address which is then translated to a main store address. Overflow detection circuitry in the ALU detects if an overflow out of the offset occurs as a result of the ALU operation for obtaining the new offset value. If an overflow is detected during the calculation of the new offset value, translation of the virtual address is subsequently aborted.

公开(公告)号：DE3071860D1

公开(公告)日：1987-01-22

申请号：DE3071860

申请日：1980-12-12

Applicant: IBM

Inventor： LEWIS DAVID OTTO ,  PERTZBORN JAMES JOHN ,  ROBINSON THOMAS SCOTT ,  HEISE NYLES NORBERT ,  HOFFMAN ROY LOUIS ,  KISS ISTVAN STEVE

IPC: G06F13/12 ,  G06F12/10 ,  G06F13/10 ,  G06F13/18

Abstract: In virtual storage data processing apparatus including real main storage, 10 a virtual address translation unit VAT 15 and a common I/O control unit 110 serving plural I/O devices, 150 the virtual address translation unit includes a resolved address register for each I/O device, a pool of resolved address registers and control logic responsive to a device specific CPU I/O command for initiating chaines I/O data transfers to cause the VAT apparatus to translate a first virtual address to be used in the chained data transfer operation and load the translated (resolved) address the appropriate resolved address register and responsive to a command from the shared control unit indicating that one of the commanded I/O devices is ready for data transfer to become nonresponsive to further CPU I/O commands and cause the VAT to resolve a succession of virtual addresses for the data transfer and to load the resolved addresses into resolved address registers of the pool whereby a data transfer operation can commence using the resolved address in the register unique to the I/O device which is first ready for data transfer and thereafter continue with data transfers using resolved addresses from the registers shared by all of the I/O devices but captured for use by the I/O device first ready for data transfer. Upon the data transfers being completed for that I/O device, the VAT resolves a succession of virtual addresses and loads them into the shared registers for use during data transfers by the next ready I/O device in response to a command from the shared I/O control unit.

公开(公告)号：DE3273912D1

公开(公告)日：1986-11-27

申请号：DE3273912

申请日：1982-03-09

Applicant: IBM

Inventor： HOFFMAN ROY LOUIS ,  HOUDEK MERLE EDWARD ,  LOEN LARRY WAYNE ,  SOLTIS FRANK GERALD

IPC: G06F9/46 ,  G06F9/48 ,  G06F15/16 ,  G06F15/177

Abstract: The task handling arrangement is provided in a multiprocessor system in which each processor (5) includes a task dispatcher and a signal dispatcher. The signal dispatcher runs in a processor whenever a task dispatching element (TDE) is put on the task dispatching queue (TDQ) as a result of the task running in the processor. The signal dispatcher examines the TDEs enqueued on the TDQ and determines if any task dispatcher should be invoked, i.e. if any processor is running a lower priority task a task switch should occur. If so, it signals the selected processor to invoke its task dispatcher. After completing the task switch, the selected processor must invoke its signal dispatcher to determine if the task it had been performing should now be performed on some other processor in the multiprocessor system.

公开(公告)号：DE2963499D1

公开(公告)日：1982-09-30

申请号：DE2963499

申请日：1979-09-24

Applicant: IBM

Inventor： MITCHELL GLEN ROBERT ,  SOLTIS FRANK GERALD ,  HOFFMAN ROY LOUIS

IPC: G06F9/34 ,  G06F9/355 ,  G06F12/02 ,  G06F12/06 ,  G06F12/10 ,  G06F13/00

Abstract: Virtual addressing apparatus for implementing a large virtual address in a computer system having narrow data paths, ALU, and local storage register arrays without requiring multiple passes. The virtual addressing apparatus stores the segment portion of a virtual address in a segment register and the offset portion of the virtual address in an offset register. To form a new virtual address, a new offset value is obtained by adding the displacement value given by the instruction in the instruction buffer register to the offset value stored in the offset register. The segment portion of the virtual address does not participate in the arithmetic operation for forming the new virtual address. The segment and offset portions are concatenated to form the new virtual address which is then translated to a main store address. Overflow detection circuitry in the ALU detects if an overflow out of the offset occurs as a result of the ALU operation for obtaining the new offset value. If an overflow is detected during the calculation of the new offset value, translation of the virtual address is subsequently aborted.

公开(公告)号：MX150980A

公开(公告)日：1984-09-03

申请号：MX18558581

申请日：1981-01-16

Applicant: IBM

Inventor： HEISE NYLES NORBERT ,  HOFFMAN ROY LOUIS ,  KISS ISTVAN STEVE ,  LEWIS DAVID OTTO ,  PERTZBORN JAMES JOHN ,  ROBINSON THOMAS-SCOTT

IPC: G06F13/12 ,  G06F12/10 ,  G06F13/10 ,  G06F13/18 ,  H04B1/00

Abstract: In virtual storage data processing apparatus including real main storage, 10 a virtual address translation unit VAT 15 and a common I/O control unit 110 serving plural I/O devices, 150 the virtual address translation unit includes a resolved address register for each I/O device, a pool of resolved address registers and control logic responsive to a device specific CPU I/O command for initiating chaines I/O data transfers to cause the VAT apparatus to translate a first virtual address to be used in the chained data transfer operation and load the translated (resolved) address the appropriate resolved address register and responsive to a command from the shared control unit indicating that one of the commanded I/O devices is ready for data transfer to become nonresponsive to further CPU I/O commands and cause the VAT to resolve a succession of virtual addresses for the data transfer and to load the resolved addresses into resolved address registers of the pool whereby a data transfer operation can commence using the resolved address in the register unique to the I/O device which is first ready for data transfer and thereafter continue with data transfers using resolved addresses from the registers shared by all of the I/O devices but captured for use by the I/O device first ready for data transfer. Upon the data transfers being completed for that I/O device, the VAT resolves a succession of virtual addresses and loads them into the shared registers for use during data transfers by the next ready I/O device in response to a command from the shared I/O control unit.

公开(公告)号：DE2963099D1

公开(公告)日：1982-08-05

申请号：DE2963099

申请日：1979-06-11

Applicant: IBM

Inventor： HOFFMAN ROY LOUIS ,  MITCHELL GLEN ROBERT ,  SOLTIS FRANK GERALD

IPC: G06F12/10 ,  G06F9/36 ,  G06F13/00 ,  G11C9/06

Abstract: Address translation apparatus is provided for translating virtual addresses to real storage addresses and real storage addresses to virtual storage addresses. The address translation apparatus uses a page directory having a next real address and an associated virtual address ordered according to real addresses. This simplifies the manner in which the input/output (I/O) handles addressing in a virtual storage computer system. When the I/O device control mechanism needs to resolve the real I/O address register, it uses the contents of that register to index into the page directory to obtain a corresponding virtual address. The corresponding virtual address is incremented and converted to a real address which is used to index into the page directory. The virtual address taken from the page directory is then compared with the virtual address which had been incremented and translated. If the two compare then the real address which had been used to access the page directory is entered into a register so as to be available as a real main storage address. In actuality it is only a partial real main storage address and is concantenated with a byte identifier portion of the main storage address which requires no translation and which was a part of the original I/O real address for main storage.

公开(公告)号：DE2702722A1

公开(公告)日：1977-08-11

申请号：DE2702722

申请日：1977-01-24

Applicant: IBM

Inventor： HOFFMAN ROY LOUIS ,  KEMPKE WILLIAM GEORGE ,  SOLTIS FRANK GERALD

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/455 ,  G06F9/20

Abstract: A special directly executable instruction, Fetch Instruction Operand Address (FIOA) is accessed in response to encountering a complex non-directly executable instruction. Execution of the FIOA instruction causes generation of control signals for address calculation of the operands in the non-directly executable instruction by the same I phase hardware used by other directly executable instructions.

公开(公告)号：DE3480129D1

公开(公告)日：1989-11-16

申请号：DE3480129

申请日：1984-02-20

Applicant: IBM

Inventor： HOFFMAN ROY LOUIS ,  HOUDEK MERLE EDWARD ,  SOLTIS FRANK GERALD

IPC: G06F12/00 ,  G06F9/46 ,  G06F9/52 ,  G06F15/16 ,  G06F15/177 ,  G06F12/14

公开(公告)号：CH634936A5

公开(公告)日：1983-02-28

申请号：CH687178

申请日：1978-06-23

Applicant: IBM

Inventor： HOFFMAN ROY LOUIS ,  KEMPKE WILLIAM GEORGE ,  MCCULLOUGH JOHN WARREN ,  SOLTIS FRANK GERALD ,  TURNER RICHARD TAD

IPC: G06F9/46 ,  G06F9/48