公开(公告)号：JP2005004733A

公开(公告)日：2005-01-06

申请号：JP2004141188

申请日：2004-05-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： JUDD IAN DAVID

IPC: G06F3/06 ,  G06F11/10 ,  G11B20/18

CPC classification number: G06F11/1076 ,  G06F2211/1007 ,  G11B20/18

Abstract: PROBLEM TO BE SOLVED: To provide a scheme for detecting a write error within a disk storage system by using a phase field.
SOLUTION: A user data block D is divided into groups 120 and a check block P is inserted after each of the groups. The check block includes a field that is updated each time a group is written. In the simplest case, the field is a single bit to be inverted. In order to more strengthen a protection, however, the field may also be a multiple bit counter to be made increment. The check block of the XOR combination of data blocks for each group or may also be XOR combination of LBA for each group.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种通过使用相位场来检测磁盘存储系统内的写入错误的方案。 解决方案：用户数据块D被划分为组120，并且在每个组之后插入校验块P. 检查块包括每次写入组时更新的字段。 在最简单的情况下，该字段是要反转的单个位。 然而，为了更加强化保护，该领域也可以是增加的多位计数器。 每个组的XOR数据块组合的检查块也可以是每个组的LOR的XOR组合。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2003216592A

公开(公告)日：2003-07-31

申请号：JP2002275672

申请日：2002-09-20

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS ,  CRADDOCK DAVID F ,  GREGG THOMAS A ,  JUDD IAN DAVID ,  PFISTER GREGORY FRANCIS ,  RECIO RENATO JOHN ,  DONALD WILLIAM SCHMIDT

IPC: G06F15/17 ,  G06F9/54 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To provide some optimizing techniques for sending a work request from a consumer to a channel adapter hardware, and method, device and program for sending a work completion to the consumer. SOLUTION: A distributed computing system having host and I/O end nodes, switches, routers and links interconnecting these components is provided. The end nodes use a pair of transmission/reception queues to transmit/receive messages. The end nodes use completion queues to inform the end user when messages have been completely sent or received and whether an error occurred during the message transmission or reception process. A mechanism for controlling the transfer of the work requests from the consumer to the channel adapter hardware by using only head pointers in the hardware is described. COPYRIGHT: (C)2003,JPO

公开(公告)号：WO2006084783B1

公开(公告)日：2007-02-22

申请号：PCT/EP2006050286

申请日：2006-01-18

Applicant: IBM ,  HYATT STEVE JOHN ,  JUDD IAN DAVID ,  NICHOLSON ROBERT BRUCE ,  QUELCH PAUL JONATHAN ,  RANDLE STEPHEN ARTHUR ,  SCALES WILLIAM JAMES

Inventor： HYATT STEVE JOHN ,  JUDD IAN DAVID ,  NICHOLSON ROBERT BRUCE ,  QUELCH PAUL JONATHAN ,  RANDLE STEPHEN ARTHUR ,  SCALES WILLIAM JAMES

IPC: G06F11/22

CPC classification number: G06F11/2289 ,  Y10T307/615

Abstract: A logic arrangement for reducing incidence of errors in connections between a power consumer apparatus and a power supply apparatus, comprises: a pattern-generating component for generating an identifiable pattern for a patterned load to be drawn from a power supply connection; a load-drawing component, responsive to the pattern-generating component, 10 for drawing the patterned load from the power supply connection; and a testing component at the power consumer apparatus for testing across a signal connection for a responsive supply to satisfy demand for the patterned load by the power supply apparatus. The logic arrangement may further be embodied as a system or as a computer program.

Abstract translation: 一种用于减少功率消耗装置和电源装置之间的连接中的误差的发生率的逻辑装置，包括：图形产生部件，用于产生用于从电源连接中抽出的图案化负载的可识别图案; 响应于图案产生部件的负载拉伸部件10，用于从电源连接中抽出图案化负载; 以及用于电力消耗装置的测试部件，用于通过用于响应电源的信号连接进行测试，以满足由电源装置对图案化负载的需求。 逻辑布置还可以体现为系统或计算机程序。

公开(公告)号：WO2005001841A3

公开(公告)日：2005-09-09

申请号：PCT/EP2004051150

申请日：2004-06-17

Applicant: IBM ,  FAIRHURST MATTHEW JOHN ,  JUDD IAN DAVID ,  SCALES WILLIAM JAMES

Inventor： FAIRHURST MATTHEW JOHN ,  JUDD IAN DAVID ,  SCALES WILLIAM JAMES

IPC: G06F3/06 ,  G06F11/10 ,  G11B20/18 ,  G11C11/00

CPC classification number: G06F11/1076 ,  G06F2211/1009 ,  G11B20/1833

Abstract: An arrangement of apparatus for safely writing data and parity to multiply-redundant storage comprises a first storage component operable to store at least a first mark in a storage device to index uniquely a pattern to be written by at least a data write; a write component operable to perform the at least data write; a further storage component operable to overwrite a mark in the storage device with at least a further mark to index uniquely a pattern to be written by a parity write; and a further write component operable to perform the parity write. Preferably, the first storage component comprises a second storage component operable to overwrite said at least first mark in said storage device with a second mark to index a pattern to be written by a first parity write; and the write component is further operable to perform the first parity write.

Abstract translation: 用于将数据和奇偶校验安全地写入多重冗余存储器的装置的布置包括：第一存储组件，可操作以将存储设备中的至少第一标记存储到唯一地通过至少数据写入要写入的模式; 写入组件，可操作以执行所述至少数据写入; 另外的存储组件可操作以用至少另外的标记覆盖存储设备中的标记，以唯一地索引要由奇偶校验写入写入的模式; 以及可操作以执行奇偶校验写入的另一写入组件。 优选地，第一存储组件包括第二存储组件，可操作以用第二标记来覆盖所述存储设备中的所述至少第一标记，以对要由第一奇偶校验写入写入的模式进行索引; 并且写入组件进一步可操作以执行第一奇偶校验写入。

公开(公告)号：WO2006084783A3

公开(公告)日：2006-12-21

申请号：PCT/EP2006050286

申请日：2006-01-18

Applicant: IBM ,  HYATT STEVE JOHN ,  JUDD IAN DAVID ,  NICHOLSON ROBERT BRUCE ,  QUELCH PAUL JONATHAN ,  RANDLE STEPHEN ARTHUR ,  SCALES WILLIAM JAMES

Inventor： HYATT STEVE JOHN ,  JUDD IAN DAVID ,  NICHOLSON ROBERT BRUCE ,  QUELCH PAUL JONATHAN ,  RANDLE STEPHEN ARTHUR ,  SCALES WILLIAM JAMES

IPC: G06F11/22

CPC classification number: G06F11/2289 ,  Y10T307/615

Abstract: A logic arrangement for reducing incidence of errors in connections between a power consumer apparatus and a power supply apparatus, comprises: a pattern-generating component for generating an identifiable pattern for a patterned load to be drawn from a power supply connection; a load-drawing component, responsive to the pattern-generating component, 10 for drawing the patterned load from the power supply connection; and a testing component at the power consumer apparatus for testing across a signal connection for a responsive supply to satisfy demand for the patterned load by the power supply apparatus. The logic arrangement may further be embodied as a system or as a computer program.

Abstract translation: 一种用于减少功率消耗装置和电源装置之间的连接中的误差的发生率的逻辑装置，包括：模式产生部件，用于产生用于从电源连接抽出的图案化负载的可识别图案; 响应于图案产生部件的负载绘图部件10，用于从电源连接中抽出图案化负载; 以及用于电力消费者装置的测试部件，用于通过用于响应电源的信号连接进行测试，以满足由电源装置对图案化负载的需求。 逻辑布置还可以被体现为系统或计算机程序。

公开(公告)号：DE69636663T2

公开(公告)日：2007-08-16

申请号：DE69636663

申请日：1996-09-19

Applicant: IBM

Inventor： JUDD IAN DAVID ,  SHAYLOR NIK ,  SYMON ALISTAIR LEASK

IPC: G06F11/20 ,  G06F15/17 ,  G06F3/06 ,  G06F11/00 ,  G06F11/10 ,  G06F13/00 ,  G06F13/12

Abstract: A system is provided for storing data for a plurality of host computers (20) on a plurality of storage arrays so that data on each storage array can be accessed by any host computer. A plurality of adapter cards (22) are used. Each adapter has controller functions for a designated storage array. There is an adapter communication interface (23) (interconnect) between all of the adapters in the system. There is also a host application interface between an application program running in the host computer and an adapter. When a data request is made by an application program to a first adapter through a host application interface for data that is stored in a storage array not primarily controlled by the first adapter, the data request is communicated through the adapter communication interface to the adapter primarily controlling the storage array in which the requested data is stored.

公开(公告)号：CA2446691A1

公开(公告)日：2003-01-09

申请号：CA2446691

申请日：2002-05-31

Applicant: IBM

Inventor： SENDELBACH LEE ANTON ,  CRADDOCK DAVID ,  JUDD IAN DAVID ,  RECIO RENATO JOHN

IPC: G06F13/10 ,  G06F13/38 ,  G06F15/17 ,  G06F13/12

Abstract: A method and system for transmitting and receiving data from a host computer system to an Ethernet adapter are provided. The method comprises establishin g a connection between the host system and the Ethernet adapter pushing a transmit or receive request message from a host system device driver to the Ethernet adapter's request queue. Access to host memory is transferred to th e Ethernet adapter. If data is being transmitted to the Ethernet adapter, the adapter reads the data from a location in host memory specified in the transmit request message, and then transmits the data onto transmission medi a (e.g. wire, fiber). If the request message is a receive request, the adapter reads the data from the media and then sends the data into host memory at th e location specified in the receive request message. When the data transfer is complete, the adapter sends a response message back to the host. The respons e message includes a transaction ID which is used by the host device driver to associate the response message to the original request message.

公开(公告)号：GB2318262B

公开(公告)日：2000-11-08

申请号：GB9620959

申请日：1996-10-08

Applicant: IBM

Inventor： BEER REGINALD ,  DEACON PETER JOHN ,  JUDD IAN DAVID ,  MORRIS NEIL

IPC: H04L12/437

Abstract: A data processing system comprises a host computer connected for the transfer of data to and from a plurality of data storage devices arranged in a string, the host computer including communication means comprising first and second ports connecting to first and second communication links, the first and second communication links being connected respectively to first and second data storage devices of said string. A bypassing means is provided between the first and second ports of the host system and the first and second data storage devices, the bypassing means being comprised of an independent bypass circuit on each of the first and second communication links between each of the first and second ports and the first and second data storage devices, the bypassing means being operable to bypass the host computer by connecting the first and second devices only when both of said independent bypass circuits detect a lack of data transfer on their respective links.

公开(公告)号：GB2343596A

公开(公告)日：2000-05-10

申请号：GB9824228

申请日：1998-11-06

Applicant: IBM

Inventor： GRAY MANDY ALEXANDER ,  PALMER MICHAEL J ,  JUDD IAN DAVID

IPC: H04L12/933 ,  H04L12/403 ,  G06F13/362

Abstract: For connecting together, in a VLSI chip, a plurality of macros which require data flow connections between each other, a simple standard interface is realised between all macros. Any number of macros can be connected together, also allowing concurrent transactions between 4 or more macros using a cross-bar switch. Each macro may be a master (capable of requesting connections), a slave (capable of receiving connections from a master) or both. The centralised inter-connect logic includes three major components: the cross-bar switch, which makes the connections between the macros, the address decoder, which determines which slave each master wishes to connect to and an arbiter, which arbitrates between the macros when two or more masters request a connection simultaneously.

公开(公告)号：GB2318262A

公开(公告)日：1998-04-15

申请号：GB9620959

申请日：1996-10-08

Applicant: IBM

Inventor： BEER REGINALD ,  DEACON PETER JOHN ,  JUDD IAN DAVID ,  MORRIS NEIL

IPC: H04L12/437

Abstract: A data processing system comprises a host computer connected for the transfer of data to and from a plurality of data storage devices arranged in a string, the host computer including communication means comprising first and second ports connecting to first and second communication links, the first and second communication links being connected respectively to first and second data storage devices of said string. A bypassing means is provided between the first and second ports of the host system and the first and second data storage devices, the bypassing means being comprised of an independent bypass circuit 70 on each of the first and second communication links between each of the first and second ports and the first and second data storage devices the bypassing means being operable to bypass the host computer (shown as a node to be protected against) by connecting the first and second devices only when both of said independent bypass circuits detect a lack of data transfer on their respective links.