公开(公告)号：EP1658639A4

公开(公告)日：2009-09-30

申请号：EP04777467

申请日：2004-07-01

Applicant: IBM

Inventor： KHATER MARWAN H ,  DUNN JAMES S ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  LIU QIZHI ,  PAGETTE FRANCOIS ,  ST ONGE STEPHEN A ,  STRICKER ANDREAS D

IPC: H01L29/732 ,  H01L21/331 ,  H01L29/10 ,  H01L29/737

CPC classification number: H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

公开(公告)号：EP1815517A4

公开(公告)日：2009-08-05

申请号：EP05820748

申请日：2005-11-10

Applicant: IBM

Inventor： KHATER MARWAN H ,  PAGETTE FRANCOIS

IPC: H01L27/082 ,  H01L21/331

CPC classification number: H01L29/66287 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/732

Abstract: Disclosed is a bipolar transistor and a method of forming the transistor, where the transistor includes a collector (12) in a substrate (10), an intrinsic base (14) above the collector, an extrinsic base adjacent the intrinsic base, and an emitter (130) above the intrinsic base. The extrinsic base includes extrinsic base implant regions (82, 172, 192) adjacent the intrinsic base, when viewed in cross-section. The transistor is formed by patterning an emitter pedestal (50) for the lower portion of the emitter on the substrate above the intrinsic base. The extrinsic base is formed in regions not protected by the emitter pedestal. Subsequently, the emitter, associated spacers (180) and a silicide region (220) are formed. The silicide, extrinsic base and emitter are all self-aligned with each other.

公开(公告)号：JP2005026689A

公开(公告)日：2005-01-27

申请号：JP2004192192

申请日：2004-06-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GREGORY G FREEMAN ,  KHATER MARWAN H ,  PAGETTE FRANCOIS

IPC: H01L29/737 ,  H01L21/331 ,  H01L21/8222 ,  H01L29/10 ,  H01L29/732

CPC classification number: H01L29/66287 ,  H01L29/1004 ,  H01L29/732

Abstract: PROBLEM TO BE SOLVED: To provide a self-adjusting bipolar transistor structure having a projecting exogenous base provided with external and internal regions with different dope densities, and to provide its manufacturing method.
SOLUTION: The first material of a first dope density is provided so that an exogenous base external region is formed. Then, a first opening is formed in the first material's layer by lithography into which a dummy emitter pedestal is formed, and by which a trench is formed between a side wall of the first opening and the dummy pedestal. Thereafter, the second material of a second dope density is provided within this trench, and another exogenous base internal extension region is formed whose projecting external base marginal part self-adjusts to a dummy pedestal marginal part. Since the emitter is formed where there were the dummy pedestals, this exogenous base also self-adjusts to the emitter.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有突出的外源基底的自调节双极晶体管结构，其具有不同的浓度密度的外部和内部区域，并提供其制造方法。 解决方案：提供第一浓度密度的第一种材料，以便形成外源基底外部区域。 然后，通过光刻法在第一材料层中形成第一开口，在其中形成有虚拟发射极基座，并且在第一开口的侧壁和虚拟基座之间形成有沟槽。 此后，在该沟槽内设置第二掺杂浓度的第二材料，并且形成另外的外源基底内部延伸区域，其突出的外部基部边缘部分自调整到虚拟基座边缘部分。 由于发射器形成在具有虚拟基座的位置，所以这种外部基极也自发地调节到发射极。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2011035393A

公开(公告)日：2011-02-17

申请号：JP2010167716

申请日：2010-07-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KHATER MARWAN H

IPC: H01L29/786 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66628 ,  H01L29/165 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684

Abstract: PROBLEM TO BE SOLVED: To provide a silicon-on-insulator (SOI) transistor having improved extension resistance and channel strain characteristics, and to provice a method of forming the SOI transistor. SOLUTION: The silicon-on-insulator (SOI) transistor device includes: a buried insulator layer formed on a bulk substrate; an SOI layer formed on the buried insulator layer; and a pair of silicon containing epitaxial regions that are disposed adjacently to opposing sides of a gate conductor and correspond to source and drain regions of the transistor device, respectively. Parts of the epitaxial regions are embedded in the buried insulator and in contact with both vertical and bottom surfaces of the SOI layer corresponding to source and drain extension regions at opposing ends of a channel region of the transistor device. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供具有改进的延伸电阻和沟道应变特性的绝缘体上硅（SOI）晶体管，并提供形成SOI晶体管的方法。 解决方案：绝缘体上硅（SOI）晶体管器件包括：形成在本体衬底上的掩埋绝缘体层; 形成在埋层绝缘体层上的SOI层; 以及一对含硅外延区域，分别与栅极导体的相对侧相邻设置并对应于晶体管器件的源极和漏极区域。 外延区域的一部分嵌入在埋入式绝缘体中并与SOI层的垂直和底表面接触，对应于在晶体管器件的沟道区的相对端处的源极和漏极延伸区域。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2006074040A

公开(公告)日：2006-03-16

申请号：JP2005247839

申请日：2005-08-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  GREGORY G FREEMAN ,  KHATER MARWAN H

IPC: H01L21/331 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L29/242 ,  H01L29/7378

Abstract: PROBLEM TO BE SOLVED: To provide a high-performance bipolar device and its manufacturing method.
SOLUTION: The method to increase electronic charge carrier mobility in a bipolar device includes the steps of generating compression strain in the device to increase hole mobility on the device's internal base, and causing tensile strain in the device to increase electron mobility on the internal base of the device. The compression strain and tensile strain are generated by forming a stress layer in the neighborhood of the internal base of the device. As for the stress layer, at least part of it is adjacent to an emitter structure of the device, and is imbedded in the device's base layer. The stress layer has a grating constant different from the internal base.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种高性能双极器件及其制造方法。 解决方案：在双极器件中增加电子载流子迁移率的方法包括以下步骤：在器件中产生压缩应变以增加器件内部基极上的空穴迁移率，并引起器件中的拉伸应变以增加电子迁移率 设备的内部基座。 压缩应变和拉伸应变通过在器件的内部基部附近形成应力层来产生。 至于应力层，其至少一部分与器件的发射极结构相邻，并嵌入器件的基极层。 应力层具有不同于内部基底的光栅常数。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005167203A

公开(公告)日：2005-06-23

申请号：JP2004291416

申请日：2004-10-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： AHLGREN DAVID C ,  GREGORY G FREEMAN ,  KHATER MARWAN H ,  VOLANT RICHARD P

IPC: H01L21/28 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732 ,  H01L29/737

CPC classification number: H01L29/66287 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7378

Abstract: PROBLEM TO BE SOLVED: To provide a bipolar transistor having self-aligned raised extrinsic base silicide and emitter contact border.
SOLUTION: The bipolar transistor exhibits the parasitic property which is more reduced than the parasitic property exhibited by a bipolar transistor which is not equipped with self-aligned silicide and a self-aligned emitter contact border. In a method of manufacturing the bipolar transistor structure, a block emitter polysilicon region is replaced with a conventional T-shaped emitter polysilicon.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有自对准凸起的外在基极硅化物和发射极接触边界的双极晶体管。 解决方案：双极晶体管表现出比由不配置自对准硅化物和自对准发射极接触边界的双极晶体管表现出的寄生特性降低的寄生特性。 在制造双极晶体管结构的方法中，块状发射极多晶硅区域被传统的T形发射极多晶硅替代。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004304190A

公开(公告)日：2004-10-28

申请号：JP2004090598

申请日：2004-03-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KHATER MARWAN H ,  RIEH JAE-SUNG ,  STRICKER ANDREAS D ,  GREGORY G FREEMAN ,  SCHONENBERG KATHRYN T

IPC: H01L29/70 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737

CPC classification number: H01L29/66287 ,  H01L29/0649 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a bipolar transistor structure, capable of reducing the parasitic capacitance.
SOLUTION: A method for forming a vertical bipolar transistor, comprising the steps of forming a bipolar transistor on silicon semiconductor substrate 11 which has an upper surface; forming STI regions 14 which are made of dielectric materials and have an inside edge portion and an upper surface, respectively; forming a doped collector region C between a pair of STI regions; also forming a counter doped intrinsic base region IB between the pair of STI regions, wherein there is each margin between the intrinsic base region and the pair of STI regions, and the intrinsic base region has edges; forming a doped-emitter region on the intrinsic base region apart from the edges; and forming shallow separated extension regions IE made of dielectric materials in the above margins, and placing them in parallel with the edges of the intrinsic base region; and forming an outer base region which covers the shallow separated extension regions partially, and further extends to the intrinsic base region, thereby physically and electrically contacting with the intrinsic base region.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：DE112012002434T5

公开(公告)日：2014-03-06

申请号：DE112012002434

申请日：2012-06-21

Applicant: IBM

Inventor： CAMILLO-CASTILLO RENATA ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  LIU QIZHI ,  GRAY PETER B ,  KHATER MARWAN H

IPC: H01L29/73

Abstract: Verfahren zum Herstellen von Bipolartransistoren, Bipolartransistoren, die mittels der Verfahren hergestellt werden, sowie Entwurfsstrukturen für einen Bipolartransistor. Der Bipolartransistor (80) beinhaltet eine dielektrische Schicht (32) auf einer intrinsischen Basis (84) und eine extrinsische Basis (82), die durch die dielektrische Schicht wenigstens teilweise von der intrinsischen Basis getrennt ist. Eine Emitter-Öffnung (52) erstreckt sich durch die extrinsische Basis und die dielektrische Schicht hindurch. Die dielektrische Schicht ist lateral relativ zu der Emitter-Öffnung vertieft, um einen Hohlraum (60a, 60b) zwischen der intrinsischen Basis und der extrinsischen Basis zu definieren. Der Hohlraum ist mit einer Halbleiterschicht (64) gefüllt, welche die extrinsische Basis und die intrinsische Basis physisch miteinander verbindet.

公开(公告)号：GB2506816B

公开(公告)日：2015-09-09

申请号：GB201401778

申请日：2012-06-21

Applicant: IBM

Inventor： CAMILLO-CASTILLO RENATA ,  GRAY PETER B ,  HARAME DAVID LOUIS ,  JOSEPH ALVIN J ,  KHATER MARWAN H ,  LIU QIZHI

IPC: H01L21/8249 ,  H01L29/732

Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.

公开(公告)号：WO2013006277A2

公开(公告)日：2013-01-10

申请号：PCT/US2012043443

申请日：2012-06-21

Applicant: IBM ,  CAMILLO-CASTILLO RENATA ,  GRAY PETER B ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  KHATER MARWAN H ,  LIU QIZHI

Inventor： CAMILLO-CASTILLO RENATA ,  GRAY PETER B ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  KHATER MARWAN H ,  LIU QIZHI

CPC classification number: H01L29/73 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/107 ,  H01L29/66272 ,  H01L29/7322

Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor (80) includes a dielectric layer (32) on an intrinsic base (84) and an extrinsic base (82) at least partially separated from the intrinsic base by the dielectric layer. An emitter opening (52) extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity (60a, 60b) between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer (64) that physically links the extrinsic base and the intrinsic base together.

Abstract translation: 用于制造双极结晶体管的方法，通过该方法制造的双极结型晶体管以及双极结型晶体管的设计结构。 双极结晶体管（80）包括在本征基极（84）上的介电层（32）和通过介电层至少部分地与本征基极分离的外部基极（82）。 发射极开口（52）延伸穿过外部基极和电介质层。 电介质层相对于发射极开口横向凹入以限定内部基极和外部基极之间的空腔（60a，60b）。 空腔填充有将外部基极和固有基底物理连接在一起的半导体层（64）。