公开(公告)号：EP1658639A4

公开(公告)日：2009-09-30

申请号：EP04777467

申请日：2004-07-01

Applicant: IBM

Inventor： KHATER MARWAN H ,  DUNN JAMES S ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  LIU QIZHI ,  PAGETTE FRANCOIS ,  ST ONGE STEPHEN A ,  STRICKER ANDREAS D

IPC: H01L29/732 ,  H01L21/331 ,  H01L29/10 ,  H01L29/737

CPC classification number: H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

公开(公告)号：EP1644973A4

公开(公告)日：2009-03-04

申请号：EP04755817

申请日：2004-06-22

Applicant: IBM

Inventor： JOSEPH ALVIN J ,  LIU QIZHI

IPC: H01L21/8222 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082 ,  H01L29/10 ,  H01L29/732

CPC classification number: H01L29/66287 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/732

Abstract: A high fT and fmax bipolar transistor (100) includes an emitter (104), a base (120), and a collector (116). The emitter has a lower portion (108) and an upper portion (1.12) that extends beyond the lower portion. The base includes an intrinsic base (140) and an extrinsic base (144). The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor (148) that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor (152) that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.

公开(公告)号：EP1979932A4

公开(公告)日：2012-03-14

申请号：EP07710130

申请日：2007-01-15

Applicant: IBM

Inventor： ERTURK METE ,  GROVES ROBERT A ,  JOHNSON JEFFREY B ,  JOSEPH ALVIN J ,  LIU QIZHI ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

IPC: H01L21/77 ,  H01L21/302 ,  H01L21/306 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1794806A4

公开(公告)日：2011-06-29

申请号：EP05798479

申请日：2005-09-20

Applicant: IBM

Inventor： GEISS PETER J ,  GRAY PETER B ,  JOSEPH ALVIN J ,  LIU QIZHI

IPC: H01L31/072

CPC classification number: H01L29/0821 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66318

公开(公告)号：JP2013048274A

公开(公告)日：2013-03-07

申请号：JP2012233911

申请日：2012-10-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： METE ERTURK ,  ROBERT A GROVES ,  JEFFREY B JOHNSON ,  ALVIN J JOSEPH ,  LIU QIZHI ,  EDMUND J SPROGIS ,  ANTHONY K STAMPER

IPC: H01L21/3205 ,  H01L21/331 ,  H01L21/768 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L23/522 ,  H01L27/06 ,  H01L29/737

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a backside contact structure and a method of fabricating the structure.SOLUTION: The method includes: forming a first dielectric layer 105 on a frontside of a substrate 100 having the frontside and an opposing backside; forming an electrically conductive first stud contact 140B in the first dielectric layer, the first stud contact extending through the first dielectric layer to the frontside of the substrate; thinning the substrate from the backside of the substrate to form a new backside of the substrate; forming a trench 165 in the substrate, the trench extending from the new backside of the substrate to the first dielectric layer, to expose a bottom surface of the first stud contact in the trench; and forming a conformal electrically conductive layer 170, 175 on the new backside of the substrate, sidewalls of the trench, exposed surfaces of the first dielectric layer and exposed surfaces of the first stud contacts, where the conductive layer is not thick enough to completely fill the trench.

Abstract translation: 要解决的问题：提供一种背面接触结构和制造该结构的方法。 解决方案：该方法包括：在具有前侧和相对的背面的基板100的前侧形成第一电介质层105; 在所述第一电介质层中形成导电的第一螺柱触头140B，所述第一螺柱触头延伸穿过所述第一电介质层到所述衬底的前侧; 从衬底的背面稀释衬底以形成衬底的新背面; 在衬底中形成沟槽165，沟槽从衬底的新背面延伸到第一介电层，以暴露沟槽中的第一柱形触头的底表面; 并且在衬底的新背面上形成共形导电层170,175，沟槽的侧壁，第一介电层的暴露表面和第一螺柱触头的暴露表面，其中导电层不够厚以至完全填充 沟渠。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2005260239A

公开(公告)日：2005-09-22

申请号：JP2005066770

申请日：2005-03-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GEISS PETER J ,  MARWAN H KHATER ,  LIU QIZHI ,  RANDY W MANN ,  PURTELL ROBERT J ,  BETHANN RAINEY ,  JAE-SUNG RIEH ,  STRICKER ANDREAS D

IPC: H01L21/28 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L29/737 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01L29/66242 ,  H01L21/28518 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/456 ,  H01L29/7371

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a hetero-junction bipolar transistor having a raised base of which the base resistance is decreased by forming silicide extending to an emitter region in a self-aligning manner on a raised base.
SOLUTION: This silicide formation is incorporated in a BiCMOS process flow after forming a raised and extrinsic base. The bipolar transistor has the raised and extrinsic base, and the hetero-junction bipolar transistor has silicide positioned on the raised and extrinsic base. The silicide on the extrinsic base extends to an emitter in a self-aligning manner. The emitter is isolated from the silicide by a spacer.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种通过在自升高的基极上以自对准的方式形成延伸到发射极区域的硅化物来提供具有升高的基极的异质结双极晶体管的方法，其中基极电阻降低。 解决方案：该硅化物形成在形成凸起和外在基体之后并入BiCMOS工艺流程中。 双极晶体管具有凸起和非本征基极，并且异质结双极晶体管具有位于升高和外部基极上的硅化物。 外在基极上的硅化物以自对准方式延伸到发射极。 发射极通过间隔物与硅化物隔离。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2006034355A2

公开(公告)日：2006-03-30

申请号：PCT/US2005033851

申请日：2005-09-20

Applicant: IBM ,  GEISS PETER J ,  GRAY PETER B ,  JOSEPH ALVIN J ,  LIU QIZHI

Inventor： GEISS PETER J ,  GRAY PETER B ,  JOSEPH ALVIN J ,  LIU QIZHI

IPC: H01L31/109

CPC classification number: H01L29/0821 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66318

Abstract: A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate (12) including at least a subcollector (13); a buried refractory metal silicide layer (28) located on the subcollector; and a shallow trench isolation region (30) located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.

Abstract translation: 提供了用于高速BiCMOS应用的异步双极晶体管（HBT），其中通过在器件的子集电极上的浅沟槽隔离区域的下面提供掩埋难熔金属硅化物层来降低集电极电阻Rc。 具体地，本发明的HBT包括至少包括子集电极（13）的基板（12）。 位于子集电极上的埋置难熔金属硅化物层（28）; 以及位于所述埋入难熔金属硅化物层的表面上的浅沟槽隔离区域（30）。 本发明还提供一种制造这种HBT的方法。 该方法包括在器件的子集电极上的浅沟槽隔离区域的下面形成埋置难熔金属硅化物。

公开(公告)号：GB2497177B

公开(公告)日：2015-02-18

申请号：GB201220384

申请日：2012-11-13

Applicant: IBM

Inventor： LIU QIZHI ,  PEKARIK JOHN JOSEPH ,  ELLIS-MONAGHAN JOHN JOSEPH ,  ADKISSON JAMES WILLIAM ,  HARAME DAVID LOUIS

IPC: H01L29/08 ,  H01L29/737

公开(公告)号：WO2013006277A2

公开(公告)日：2013-01-10

申请号：PCT/US2012043443

申请日：2012-06-21

Applicant: IBM ,  CAMILLO-CASTILLO RENATA ,  GRAY PETER B ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  KHATER MARWAN H ,  LIU QIZHI

Inventor： CAMILLO-CASTILLO RENATA ,  GRAY PETER B ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  KHATER MARWAN H ,  LIU QIZHI

CPC classification number: H01L29/73 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/107 ,  H01L29/66272 ,  H01L29/7322

Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor (80) includes a dielectric layer (32) on an intrinsic base (84) and an extrinsic base (82) at least partially separated from the intrinsic base by the dielectric layer. An emitter opening (52) extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity (60a, 60b) between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer (64) that physically links the extrinsic base and the intrinsic base together.

Abstract translation: 用于制造双极结晶体管的方法，通过该方法制造的双极结型晶体管以及双极结型晶体管的设计结构。 双极结晶体管（80）包括在本征基极（84）上的介电层（32）和通过介电层至少部分地与本征基极分离的外部基极（82）。 发射极开口（52）延伸穿过外部基极和电介质层。 电介质层相对于发射极开口横向凹入以限定内部基极和外部基极之间的空腔（60a，60b）。 空腔填充有将外部基极和固有基底物理连接在一起的半导体层（64）。

公开(公告)号：WO2007084879A3

公开(公告)日：2008-02-21

申请号：PCT/US2007060544

申请日：2007-01-15

Applicant: IBM ,  ERTURK METE ,  GROVES ROBERT A ,  JOHNSON JEFFREY B ,  JOSEPH ALVIN J ,  LIU QIZHI ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

Inventor： ERTURK METE ,  GROVES ROBERT A ,  JOHNSON JEFFREY B ,  JOSEPH ALVIN J ,  LIU QIZHI ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

IPC: H01L21/00 ,  H01L21/302 ,  H01L21/306 ,  H01L21/44 ,  H01L21/77

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation (250) in a substrate (100), the substrate (100) having a frontside and an opposing backside; forming a first dielectric layer (105) on the frontside of the substrate (100); forming a trench (265C) in the first dielectric layer (105), the trench (265C) aligned over and within a perimeter of the dielectric isolation (250) and extending to the dielectric isolation (250); extending the trench (265C) formed in the first dielectric layer (1 05) through the dielectric isolation (250) and into the substrate (1 00)to a depth (Dl ) less than a thickness of the substrate (1 00); filling the trench (265C) and co-planarizing a top surface of the trench (265C) with a top surface of the first dielectric layer (1 05) to form an electrically conductive through via (270C); and thinning the substrate (100) from a backside of the substrate (100) to expose the through via (270C).

Abstract translation: 背面接触结构及其制造方法。 该方法包括：在衬底（100）中形成绝缘隔离（250），所述衬底（100）具有前侧和相对的背面; 在所述基板（100）的前侧形成第一介电层（105）; 在所述第一电介质层（105）中形成沟槽（265C），所述沟槽（265C）在所述电介质隔离（250）的周边内并且在所述绝缘隔离（250）的周边内并且延伸到所述电介质隔离（250）; 将形成在第一电介质层（105）中的沟槽（265C）延伸通过电介质隔离（250）并延伸到衬底（100）中至小于衬底厚度（001）的深度（D1）。 填充沟槽（265C）并且将沟槽（265C）的顶表面与第一介电层（105）的顶表面共平面化以形成导电通孔（270C）; 以及从所述衬底（100）的背面使所述衬底（100）变薄以暴露所述通孔（270C）。