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    Arithmetic and logical unit with error checking
    1.
    发明授权
    Arithmetic and logical unit with error checking 失效
    具有错误检查的算术和逻辑单元

    公开(公告)号：US3649817A

    公开(公告)日：1972-03-14

    申请号：US3649817D

    申请日：1970-07-29

    Applicant: IBM

    Inventor： KELLER GUNTER ,  KNAUFT GUENTER ,  SKUIN PETAR ,  VOGT EDWIN

    IPC: G06F7/38 ,  G06F7/00 ,  G06F7/499 ,  G06F7/508 ,  G06F11/10 ,  H03K19/00

    CPC classification number: G06F11/10

    Abstract: In an arithmetic and logical unit suitable for ''''Adding,'''' ''''AND,'''' ''''OR'''' and ''''Exclusive OR'''' operations, additions are performed to the carry-dependent sum formation principle, while during the execution of logical operations, operand bit parity functions related to the respective operation are generated by means of a function generator. In an operation-dependent checking circuit the carries of additions or the parity functions of logical operations are combined for result parity prediction independently of the sum formed. For error-checking the result, the parity of the result bits is compared for compliance with the predicted parity.

    Abstract translation: 在适用于“添加”，“与”，“或”和“异或”运算的算术和逻辑单元中，对进位依赖和形成原理进行加法，而在执行逻辑运算期间，操作数位奇偶校验函数 通过函数发生器产生与相应操作有关的信息。 在与操作相关的检查电路中，独立于形成的和，将逻辑运算的加法或奇偶校验功能的组合用于结果奇偶校验。 为了错误检查结果，比较结果位的奇偶校验符合预测的奇偶校验。

    2.
    发明专利
    未知

    公开(公告)号：DE2842750A1

    公开(公告)日：1980-04-10

    申请号：DE2842750

    申请日：1978-09-30

    Applicant: IBM DEUTSCHLAND

    Inventor： HAJDU JOHANN ,  KNAUFT GUENTER

    IPC: G01R31/28 ,  G01R31/3185 ,  G01T7/00 ,  G06F11/26 ,  G11C29/00 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G11C19/00

    Abstract: An LSI integrated semiconductor circuit system comprised of a plurality of interconnected minimum replaceable units. The system and each minimum replaceable unit fully conforms to the Level Sensitive Scan Design (LSSD) Rules. [Level Sensitive Scan Design Rules are fully disclosed and defined in each of the following U.S. Pat. Nos. 3,783,254, 3,761,695, 3,784,907 and in the publication "A Logic Design Structure For LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Automation Conference Proceedings, IEEE Computer Society, June 20-22, 1977, pages 462-467, New Orleans, La.]. Each of the minimum replaceable units includes a shift register segment having more than two shift register stages. Each register stage of each shift register segment of each minimum replaceable unit includes a master flip-flop (latch) and a slave flip-flop (latch). Connection means is provided for connecting the shift register segments of said minimum replaceable units into a single shift register. Additional controllable circuit means including test combinational circuit means is provided for setting a predetermined pattern in only said first two stages of each shift register segment of said minimum replaceable units. The additional circuit means facilitates and is utilized in testing the circuit integrity (stuck faults and continuity) of each minimum replaceable unit.

    METHOD AND ARRANGEMENT OF TESTING SEQUENTIAL CIRCUITS REPRESENTED BY MONOLITHICALLY INTEGRATED SEMICONDUCTOR CIRCUITS
    5.
    发明专利
    METHOD AND ARRANGEMENT OF TESTING SEQUENTIAL CIRCUITS REPRESENTED BY MONOLITHICALLY INTEGRATED SEMICONDUCTOR CIRCUITS 未知

    公开(公告)号：CA1126413A

    公开(公告)日：1982-06-22

    申请号：CA333041

    申请日：1979-08-02

    Applicant: IBM

    Inventor： HAJDU JOHANN ,  KNAUFT GUENTER

    IPC: G01R31/28 ,  G01R31/3185 ,  G01T7/00 ,  G06F11/26 ,  G11C29/00 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G06F15/20

    Abstract: An LSI monolithically integrated semiconductor circuit consisting of sequential circuits and combinational circuits contains a considerable number of storage elements designed as latches which for error detection are assembled into a shift register. If a sequential circuit thus built of several minimum replaceable units is error checked according to the invention no major additional process steps in the form of further terminals and connecting pins to a module representing the minimum replaceable unit will be required. As disclosed by the invention, by minor modification of the respective input circuits in the minimum replaceable units, the first two shift register stages of a respective minimum replaceable unit are first brought into their respective complementary states. Then the shift register contents are read out in a conventional manner, with the bit positions represented respectively by the first two shift registers in all minimum replaceable units being examined at the shift output for bit equality. If bit equality is found it can be concluded that the directly preceding minimum replaceable unit shows a stuck fault. After the defective minimum replaceable unit has been exchanged the stuck fault test is repeated so a to be able to isolate any other stuck faults that might precede that minimum replaceable unit.

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