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    DENSE CHEVRON finFET AND METHOD OF MANUFACTURING SAME
    2.
    发明公开
    DENSE CHEVRON finFET AND METHOD OF MANUFACTURING SAME 审中-公开
    密集的雪佛龙和工艺的FinFET用于生产

    公开(公告)号：EP1935020A4

    公开(公告)日：2009-08-12

    申请号：EP06825028

    申请日：2006-09-19

    Applicant: IBM

    Inventor： BEINTNER JOCHEN ,  LUDWIG THOMAS ,  NOWAK EDWARD J

    IPC: H01L21/84 ,  H01L21/336 ,  H01L27/12 ,  H01L29/78

    CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

    Abstract: A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.

    FIELD EFFECT TRANSISTOR WITH RAISED SOURCE/DRAIN FIN STRAPS
    4.
    发明申请
    FIELD EFFECT TRANSISTOR WITH RAISED SOURCE/DRAIN FIN STRAPS 审中-公开
    具有提高源/漏极鳍的场效应晶体管

    公开(公告)号：WO2008033982A2

    公开(公告)日：2008-03-20

    申请号：PCT/US2007078366

    申请日：2007-09-13

    Applicant: IBM ,  ANDERSON BRENT A ,  LUDWIG THOMAS ,  NOWAK EDWARD J

    Inventor： ANDERSON BRENT A ,  LUDWIG THOMAS ,  NOWAK EDWARD J

    IPC: H01L29/76

    CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66613 ,  H01L29/66795 ,  H01L2029/7858

    Abstract: Therefore, disclosed above are embodiments of a multi-fin field effect transistor structure (300 or 400) (e.g., a multi-fin dual-gate FET or tri-gate FET) that provides low resistance strapping of the source/drain regions (41, 42) of the fins (60a-c), while also maintaining low capacitance to the gate (80) by raising the level of the straps (71, 72) above the level of the gate (80). Embodiments of the structure of the invention incorporate either conductive vias (31, 32) (see structure 300) or taller source/drain regions (see structure 400) in order to electrically connect the source/drain straps (71, 72) to the source/drain regions (41, 42) of each fin (60a-c). Also, disclosed are embodiments of associated methods of forming these structures.

    Abstract translation: 因此，上面公开的是提供源极/漏极区域（41）的低电阻贴片的多鳍场效应晶体管结构（300或400）（例如，多鳍双栅极FET或三栅极FET）的实施例 ，42）的翅片（60a-c），同时通过将带（71,72）的电平提高到门（80）的高度以上，同时保持对门（80）的低电容。 本发明的结构的实施例包括导电通孔（31,32）（见结构300）或更高的源极/漏极区域（参见结构400），以将源极/漏极带（71,72）电连接到源极 /漏区（41,42）。 此外，公开了形成这些结构的相关方法的实施例。

    DENSE CHEVRON finFET AND METHOD OF MANUFACTURING SAME
    5.
    发明申请
    DENSE CHEVRON finFET AND METHOD OF MANUFACTURING SAME 审中-公开
    DENSE CHEVRON finFET及其制造方法

    公开(公告)号：WO2007035788A3

    公开(公告)日：2008-11-20

    申请号：PCT/US2006036575

    申请日：2006-09-19

    Applicant: IBM ,  BEINTNER JOCHEN ,  LUDWIG THOMAS ,  NOWAK EDWARD J

    Inventor： BEINTNER JOCHEN ,  LUDWIG THOMAS ,  NOWAK EDWARD J

    IPC: H01L21/00

    CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

    Abstract: A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.

    Abstract translation: 用于形成finFET的方法，结构和取向程序。 该方法包括：用第一掩模限定finFET的第一鳍片，并用第二掩模限定finFET的第二鳍片。 该结构包括单晶半导体材料的整体第一和第二鳍片以及第一和第二鳍片的纵向轴线在相同的晶体方向上排列但彼此偏移。 对准过程包括同时将栅极掩模上的对准标记对准由通过用于限定第一鳍片的第一掩模单独形成的对准靶和用于限定第二鳍片的第二掩模。

    MULTI-HEIGHT FINFETS
    6.
    发明申请
    MULTI-HEIGHT FINFETS 审中-公开
    多高熔点金属

    公开(公告)号：WO2004100290A3

    公开(公告)日：2005-02-24

    申请号：PCT/US2004002647

    申请日：2004-01-30

    Applicant: IBM ,  RAINEY BETH ANN ,  NOWAK EDWARD J ,  ALLER INGO DR ,  KEINERT JOACHIM ,  LUDWIG THOMAS

    Inventor： RAINEY BETH ANN ,  NOWAK EDWARD J ,  ALLER INGO DR ,  KEINERT JOACHIM ,  LUDWIG THOMAS

    IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/772

    CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66795

    Abstract: The present invention provides a FinFET device that has a first fin and a second fin. Each fin has a channel region and source and drain regions that extend from the channel region. The fins have different heights. The invention has a gate conductor positioned adjacent the fins. The gate conductor runs perpendicular to the fins and crosses the channel region of each of the first fin and second fin. The fins are parallel to one another. The ratio of the height of the first fin to the height of the second fin comprises a ratio of one to 2/3. The ratio is used to tune the performance of the transistor and determines the total channel width of the transistor.

    Abstract translation: 本发明提供一种具有第一鳍片和第二鳍片的FinFET器件。 每个散热片具有从沟道区延伸的沟道区和源极和漏极区。 翅片具有不同的高度。 本发明具有邻近散热片定位的栅极导体。 栅极导体垂直于翅片延伸并与第一鳍片和第二鳍片中的每一个的沟道区域交叉。 翅片彼此平行。 第一翅片的高度与第二翅片的高度的比率为1/2/3的比例。 该比率用于调整晶体管的性能并确定晶体管的总通道宽度。

    Method and device for automated layer generation for double-gate finfet design
    8.
    发明专利
    Method and device for automated layer generation for double-gate finfet design 有权
    用于双栅极FinFET设计的自动层生成的方法和装置

    公开(公告)号：JP2005197685A

    公开(公告)日：2005-07-21

    申请号：JP2004370239

    申请日：2004-12-21

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： ALLER INGO ,  GERNHOEFER VEIT ,  KEINERT JOACHIM ,  LUDWIG THOMAS

    IPC: G03F1/08 ,  G06F17/50 ,  H01L21/336 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/08 ,  H01L27/088 ,  H01L29/786

    CPC classification number: H01L29/785 ,  G06F17/5068 ,  H01L21/823821 ,  H01L29/66795

    Abstract: PROBLEM TO BE SOLVED: To provide a reliable method and a device which enable design-keeping transition from an existing non-fin design structure to a functionally identical structure based on a technology of a double-gate fin-base field-effect transistor FinFET in a metal-oxide semiconductor MOS, a device of a complementary metal-oxide semiconductor CMOS, and designing chips of the semiconductors. SOLUTION: The corresponding cell structure "C" 512 contains an arrangement of a cell structure "A" and a cell structure "B" that include no previously generated fins. Consideration is made on arrangement combinations of a cell structure "A" and a cell structure "B" generated in this design hierarchy to other cell structures. A fin generation tool decides not to arrange the fins in the cell structure "A" and cell structure "B" in this hierarchy. The fin generation is delegated to the hierarchy, thus revealing a combined fin shape 560 without steps as indicated by a circle. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种可靠的方法和装置，其使得能够基于双栅极鳍基场场效应技术将设计保持从现有非鳍设计结构转换到功能相同的结构 金属氧化物半导体MOS中的晶体管FinFET，互补金属氧化物半导体CMOS的器件，以及半导体的芯片的设计。 解决方案：相应的单元结构“C”512包含单元结构“A”和单元结构“B”的布置，其不包括先前生成的散热片。 考虑在该设计层级中生成的单元结构“A”和单元结构“B”与其它单元结构的组合。 翅片生成工具决定不将散热片排列在该层次结构中的单元结构“A”和单元结构“B”。 翅片一代被委托给层级，从而显示出一个组合的翅片形状560，没有由圆圈指示的步骤。 版权所有（C）2005，JPO＆NCIPI

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