公开(公告)号：EP1711966A4

公开(公告)日：2011-02-16

申请号：EP04704467

申请日：2004-01-22

Applicant: IBM

Inventor： BEINTNER JOCHEN ,  CHIDAMBARRAO DURESETI ,  DIVKARUNI RAMACHANDRA

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/78642 ,  H01L21/2257 ,  H01L29/66787

公开(公告)号：EP1935020A4

公开(公告)日：2009-08-12

申请号：EP06825028

申请日：2006-09-19

Applicant: IBM

Inventor： BEINTNER JOCHEN ,  LUDWIG THOMAS ,  NOWAK EDWARD J

IPC: H01L21/84 ,  H01L21/336 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.

公开(公告)号：JP2004088098A

公开(公告)日：2004-03-18

申请号：JP2003287154

申请日：2003-08-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHUDZIK MICHAEL P ,  BEINTNER JOCHEN ,  RAMACHANDORA DEIVAKARUNI ,  JAMMY RAJARAO

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10867 ,  H01L27/10841 ,  H01L29/66181

Abstract: PROBLEM TO BE SOLVED: To provide a method to form a three-dimensional electrical structure which brings two circuit elements separated in the horizontal and vertical directions into contact, regarding the formation of structures including a DRAM cell comprising a vertical transistor.
SOLUTION: A temporary insulator layer is deposited, and a vertical spacer is formed on the trench walls above the temporary insulator, then the insulator is removed to expose the substrate walls. Next, dopant is diffused into the substrate walls to form a self-aligned extension of a buried strap, and a final gate insulator is deposited, then the upper portion of a DRAM cell is formed.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2007133395A

公开(公告)日：2007-05-31

申请号：JP2006294951

申请日：2006-10-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LIEBMANN LARS W ,  BEINTNER JOCHEN

IPC: G03F1/08 ,  H01L21/027 ,  H01L21/82

CPC classification number: G03F1/70

Abstract: PROBLEM TO BE SOLVED: To provide a mask design for a sidewall image transfer process that compensates disadvantages upon forming an integrated circuit by a photolithography mask. SOLUTION: An edge based image transfer process includes depositing an etch-masking medium, for example, a nitride on the sidewall of a mesa and removing the mesa so as to leave the sidewall structure. A method is provided for converting an integrated circuit design into a set of masks for fabrication of an integrated circuit that optimizes use of the edge base imaged transfer mask process. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供用于通过光刻掩模形成集成电路来补偿缺点的侧壁图像转印工艺的掩模设计。 解决方案：基于边缘的图像转移过程包括在台面的侧壁上沉积蚀刻掩蔽介质，例如氮化物，并去除台面，以便离开侧壁结构。 提供了一种用于将集成电路设计转换成用于制造集成电路的一组掩模的方法，该集成电路优化了边缘基底成像传送掩模处理的使用。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JPH11176930A

公开(公告)日：1999-07-02

申请号：JP26992298

申请日：1998-09-24

Applicant: SIEMENS AG ,  IBM

Inventor： GRUENING ULRIKE ,  BEINTNER JOCHEN ,  RADENS CARL

IPC: H01L21/76 ,  H01L21/308 ,  H01L21/31 ,  H01L21/316 ,  H01L21/318 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a layer which is uniform in flatness and thickness on a semiconductor chip or on a semiconductor device provided with a trench. SOLUTION: An oxide thermal pad layer 104 is formed on a semiconductor substrate 102 through a thermal oxidation method, a nitride insulating layer 106, a buffer layer 108 of oxide or preferably TEOS(tetraethyl oxosilane), and a SiN mask layer 110 are formed thereon through a CVD(chemical vapor deposition) method, and a hard mask layer 112 containing BSG(borosilicate glass) or TEOS is formed on the mask layer 110. Then, a semiconductor device is manufactured, a trench is provided to the device, filler is filled, a polishing is carried out up to a pad stop, and an etching operation is carried out using the buffer layer as an etching stopper for removing the pad stop and the buffer layer, whereby a surface layer which is nearly flat and uniform in thickness can be obtained.

公开(公告)号：JP2000040797A

公开(公告)日：2000-02-08

申请号：JP17017799

申请日：1999-06-16

Applicant: SIEMENS AG ,  IBM ,  TOSHIBA CORP

Inventor： RENGARAJAN RAJESH ,  INOUE HIROFUMI ,  SRINIVASAN RADHIKA ,  BEINTNER JOCHEN

IPC: H01L21/76 ,  H01L21/762 ,  H01L27/08

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming semiconductor elements, which are electrically insulated from each other within a silicon base body, and a semiconductor structure manufactured by this method. SOLUTION: This method of forming semiconductor elements is executed by having trenches formed in the selected regions of a silicon base body 10 and depositing a barrier material on the sidewalls of the trenches. The barrier material is removed from the first sidewall parts 34 of the trenches, while the barrier material is left on the second sidewall parts 32 of the trenches and a barrier layer 26 is formed in each trench. A dielectric material 38 is deposited in the trenches and the dielectric material is deposited on each of the exposed first sidewall parts within the trenches and the barrier layers within the trenches. The dielectric material is annealed in an oxidizing atmosphere and is highly compacted, and the second sidewall parts of the trenches are prevented from being oxidized by the barrier layers. A plurality of the semiconductor elements are formed within the silicon base body, and the elements are electrically insulated from each other by the dielectric material.

公开(公告)号：JPH11330402A

公开(公告)日：1999-11-30

申请号：JP9246899

申请日：1999-03-31

Applicant: SIEMENS AG ,  IBM

Inventor： GRUENING ULRIKE ,  JAIPRAKASH VENKATACHALAM C ,  BRONNER GARY ,  RADENS CARL ,  BEINTNER JOCHEN

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To reduce the diffusion of the height of an embedded strap by making the depression extending below the surface of the substrate in a filling material, to determine the top surface of a buried strap and by making a recess extending below the top surface of the embedded strap in a collar to determine the bottom side surface. SOLUTION: A substrate includes a partially completed trench capacitor. A collar 110 is made on the upper portion of the trench capacitor. A trench 108 is filled with a filling material 112 and the inner sidewall of the collar is lined with the filling material 112. A recess having a predetermined depth is made in the filling material 112. The depth of the recess actually determines the top portion of an embedded strap. A hole is made in the collar to the depth of 120 below the top surface 118 of the filling material 112. A layer 122 is removed from the side of the trench 108 and the top surface of a semiconductor device 100, while a recessed region 124 filled with the material of the layer 122 is left.

公开(公告)号：JP2005197749A

公开(公告)日：2005-07-21

申请号：JP2005002025

申请日：2005-01-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEINTNER JOCHEN ,  DIVAKARUNI RAMA ,  JAMMY RAJARAO

IPC: H01L21/8242 ,  H01L21/762 ,  H01L27/108 ,  H01L29/76

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10894

Abstract: PROBLEM TO BE SOLVED: To provide a structure for a perpendicular-type DRAM capable of being integrated into a process flow, using a flat surface device.
SOLUTION: A method of manufacturing an integrated circuit device comprises steps of etching a trench in a substrate; and forming DRAM cells which include a build-up capacitor 24 at a lower edge and a perpendicular-type MOSFET having a gate conductor 30 covering the build-up capacitor 24 and a boron doped channel. The method further comprises a step of forming a trench adjacent to the DRAM cells and a silicon acid nitriding isolation liner at either side of the DRAM cells. Next, an isolation region is formed in the trench at either side of the DRAM cells. Thereafter, the DRAM cells, including a boron-containing channel region are exposed to a high temperature caused by heat treatment to form a supporting device and so on. A nitride containing isolation liner reduces the isolation of boron in a channel region as compared with an oxide-containing isolation liner essentially without nitrogen.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种能够使用平面装置集成到工艺流程中的垂直型DRAM的结构。 解决方案：一种制造集成电路器件的方法包括以下步骤：蚀刻衬底中的沟槽; 并且在下边缘处形成包括积聚电容器24的DRAM单元和具有覆盖积层电容器24的栅极导体30和掺杂硼的沟道的垂直型MOSFET。 该方法还包括在DRAM单元的任一侧形成与DRAM单元相邻的沟槽和硅酸氮化隔离衬垫的步骤。 接下来，在DRAM单元的任一侧的沟槽中形成隔离区。 此后，包括含硼沟道区的DRAM单元暴露于由热处理引起的高温以形成支撑装置等。 与基本上不含氮的含氧化物的隔离衬垫相比，含氮化物的隔离衬垫减少了沟道区域中硼的分离。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2000323684A

公开(公告)日：2000-11-24

申请号：JP2000085406

申请日：2000-03-24

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： GRUENING ULRIKE ,  HALLE SCOTT ,  RADENS CARL J ,  JEFFREY J WERSER ,  BEINTNER JOCHEN ,  MANDELMAN JACK A ,  WITTMANN JUERGEN

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To form a trench capacitor in a semiconductor body. SOLUTION: A trench capacitor 10 and a MOS transistor 9 are provided in a substrate 16 to form a cell 8 of the DRAM, and the cell 8 is separated from adjacent cells by an STI region 28. The capacitor 10 is composed of an insulator 14 enveloping the trench and a first electrode 24 filled with polysilicon 12, is connected to the drain portion 72 through a buried electrode 22, and is insulated from a gate electrode 20 by a dielectric 23. A second electrode 25 is formed in its bottom portion through an insulator 14. A transistor 9 has N-type drain 72 and source 71 in an upper active region 11 of the substrate 16 and operates with a p well as channel.

公开(公告)号：WO0199164A3

公开(公告)日：2002-07-25

申请号：PCT/US0119660

申请日：2001-06-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： LEE GILL YONG ,  HALLE SCOTT D ,  BEINTNER JOCHEN

IPC: G03F7/09 ,  H01L21/027 ,  H01L21/311 ,  H01L21/314 ,  H01L21/8242 ,  H01L21/033 ,  H01L21/32

CPC classification number: H01L21/0276 ,  G03F7/091 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/3145 ,  H01L27/10861

Abstract: In accordance with the present invention, a method for employing and removing inorganic anti-reflection coatings, includes the steps of providing a first dielectric layer (122) on a semiconductor device (110) structure to be processed, the first dielectric layer being selectively removable relative to the semiconductor device structure, and forming an inorganic dielectric anti-reflection coating (DARC) (124) on the first dielectric layer, the DARC being selectively removable relative to the first dielectric layer. A resist layer (130) is patterned on the DARC. The resist is selectively removable relative to the DARC. The semiconductor device structure is etched, and the resist layer, the DARC and the first dielectric layer are selectively removed.

Abstract translation: 根据本发明，一种采用和去除无机抗反射涂层的方法包括以下步骤：在要加工的半导体器件（110）结构上提供第一介电层（122），所述第一介电层可选择性地可移除 相对于半导体器件结构，以及在第一电介质层上形成无机介电抗反射涂层（DARC）（124），所述DARC可相对于第一介电层选择性地去除。 抗蚀剂层（130）在DARC上被图案化。 抗蚀剂相对于DARC有选择性地可去除。 蚀刻半导体器件结构，并且选择性地去除抗蚀剂层，DARC和第一介电层。