公开(公告)号：JP2002073412A

公开(公告)日：2002-03-12

申请号：JP2001213766

申请日：2001-07-13

Applicant: IBM

Inventor： DHONG SANG HOO ,  HOFSTEE HARM PETER ,  TAKAHASHI OSAMU ,  LUNTEREN JAN VAN

IPC: G06F12/02 ,  G06F12/06

Abstract: PROBLEM TO BE SOLVED: To disclose a method to implement an address mapping for a memory in a computer system. SOLUTION: The memory is composed of several memory banks and each memory bank identifies itself with each bank number. A block address component of a physical address is converted into a corresponding bank number and a related internal bank address. The bank number is constituted by connecting a fist lookup table output with a second lookup table output. The output of the first table is obtained by a first segment X1 and a second segment Y1 of the block address component and the output of the second table is obtained by a third segment X2 and a fourth segment Y2 of the block address component. Data saved at a specified location can be accessed by means of the bank number and the related internal bank address.

公开(公告)号：JP2002033769A

公开(公告)日：2002-01-31

申请号：JP2001155823

申请日：2001-05-24

Applicant: IBM

Inventor： LUNTEREN JAN VAN

IPC: G06F17/30 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To provide a system for evaluating a fixed retrieve key for the unit of segment by retrieving all over a tree structure table without fail, for detecting output information which corresponds to the longest matching prefix. SOLUTION: Concerning at least one segment, only the selected bit of a retrieve key segment is used as an index for accessing a relational table preserving a test value to be compared with an individual retrieve key segment. The bit to be selected is determined by an index mask, while being reflected with the variance of valid test values (and valid retrieve key segment values) in a table entry. This enables table compression, for minimizing required storage conditions and retrieval time. A procedure is disclosed for generating the optimal index mask in response to the set of the valid test value.

公开(公告)号：GB2515755A

公开(公告)日：2015-01-07

申请号：GB201311786

申请日：2013-07-01

Applicant: IBM

Inventor： NG HOI SUN ,  LUNTEREN JAN VAN

IPC: G06F17/14

Abstract: A method for performing an FFT computation, comprising: providing first and second input data elements in multiple memory areas of a memory unit (3); in each of a number of consecutive computation stages, performing multiple butterfly operations each based on one first input data element and one second input data element to obtain two output data elements, wherein first and second input data elements for a plurality of the multiple butterfly operations are each simultaneously retrieved from predetermined memory locations of a first and a second of the memory areas of the memory unit; for each of the computation stages, storing the two output data elements in the memory unit (3) as the input data elements for a next computation stage accord­ing to a mapping scheme, wherein the mapping scheme is configured to store the output data elements at mem­ory locations in the first and second memory areas, so that they are simultaneously retrievable as input data elements for a plurality of butterfly operations of the subsequent computation stage.

公开(公告)号：GB2461648A

公开(公告)日：2010-01-13

申请号：GB0913415

申请日：2009-08-03

Applicant: IBM

Inventor： SCHLIPF THOMAS ,  FRITZ ROLF ,  SMITH CHRISTOPHER S ,  MAYER ULRICH ,  LUNTEREN JAN VAN

IPC: G05B19/045

Abstract: A system stores an input compare vector in an input compare vector table. The system also stores an output vector, a next state value and a next state start address in an output vector, next state, next state address table. Each comparator compares each input compare vector from the input compare vector table and an external input vector, and outputs a selection signal to a multiplexer. The multiplexer associates the selection signals with an offset value, and provides the offset value to adder logic. The adder logic adds the offset value and an address from a current state start address register. A result of the addition is used as an address to access a row in the output vector, next state, next state address table. The accessed row has an output vector, a next state value and a next state start address corresponding to a current state and the external input vector.

公开(公告)号：GB2461649A

公开(公告)日：2010-01-13

申请号：GB0913420

申请日：2009-08-03

Applicant: IBM

Inventor： SCHLIPF THOMAS ,  FRITZ ROLF ,  SMITH CHRISTOPHER S ,  MAYER ULRICH ,  LUNTEREN JAN VAN

IPC: G05B19/045

Abstract: Preventing a communication loop in communicating finite state machines by providing two tables, an output next state (OTNS) table and a communication output (COUT) table. The OTNS table is divided into two array data structures, an input compare vector (ICVT1) and an output next state next address table (ONNT). The COUT table is divided into two array data structures, an input compare vector (ICVT2) and a communication output table (COMCONT). Input compare vectors in the ICVT1 are retrieved and fed into comparators. The comparators compare the retrieved input compare vectors with an input signal. When a match is found, a corresponding comparator sets a corresponding selection signal to a pre-determined value to generate an offset value through a multiplexer. An adder adds the offset value and a value stored in a current state start address (CSSA) register, and generates an adding result. The adding result is used as an address to access a row in the ONNT. There is state transition information in that row of the ONNT.

公开(公告)号：AU2003255288A1

公开(公告)日：2004-04-30

申请号：AU2003255288

申请日：2003-06-26

Applicant: IBM

Inventor： LUNTEREN JAN VAN

IPC: H04L12/66 ,  H04L12/743 ,  H04L29/06 ,  H04L12/56

Abstract: A method and apparatus for deep packet processing including a parsing and a searching method supported by a data structure storing the state-transition rules in the state-transition rule tables of a programmable state machine for parsing. The state-transition rule table is then compressed using the BaRT compression algorithm. Each transition rule comprises a test value, a test mask and a next state field. In a second embodiment the state-transition rule table is split into more than one state-transition rule table corresponding to disjoints state spaces, thus allowing more flexibility in the use of storage space. Finally a parsing and searching method can be implemented using the same hardware. The searching and parsing methods can be implemented alternatively or in any combination at wire-speed.

公开(公告)号：GB2530261A

公开(公告)日：2016-03-23

申请号：GB201416304

申请日：2014-09-16

Applicant: IBM

Inventor： GIEFERS HEINER ,  LUNTEREN JAN VAN

IPC: G06F15/78 ,  G06F15/82

Abstract: A data processing system has data processing functionality in an execution unit, which is integrated into the memory system. An access processor sends data stored in the memory to the execution unit for processing. The access processor may send a tag with the data, identifying whether it is an operand or a configuration. The access processor uses the length of time taken to carry out the data processing operations in order to reserve time slots for the execution unit to write its results back into the memory. The access unit may send program information to the execution unit in order to configure it. The execution unit may be implemented as a field programmable gate array (FPGA). The memory may have a more than one execution unit and the some execution units may be more tightly coupled to the memory than others.

公开(公告)号：GB2519801A

公开(公告)日：2015-05-06

申请号：GB201319217

申请日：2013-10-31

Applicant: IBM

Inventor： LUNTEREN JAN VAN

IPC: G06F9/38

Abstract: A processing device 1 comprises an execute processor 2 for executing data processing instructions, and an access processor 3 to be coupled with a memory system 4 and for executing memory access instructions, where the execute processor and the access processor are logically sepa­rated units, where the execute processor has an execute processor input register file 21 with input registers 25, where a data processing instruction is executed as soon as all operands for the re­spective data processing instruction are available in the input registers. Input registers in which read data is to be written may be addressed via a read data tag provided by the access processor. Availability of operands in the input registers may be indicated by data valid flags. Result or output data may be written to memory via a write buffer 7, and may be prioritized over any further memory accesses. The access processor may be directly coupled to the execute processor input register file to directly transmit internal instructions. One or more execute processors may handle a plurality of execution threads. The access processor and memory system may be logically integrated. Ultimately, the device may effectively hide memory latency from the processor execution.

公开(公告)号：GB2461648B

公开(公告)日：2014-05-07

申请号：GB0913415

申请日：2009-08-03

Applicant: IBM

Inventor： SCHLIPF THOMAS ,  FRITZ ROLF ,  SMITH CHRISTOPHER S ,  MAYER ULRICH ,  LUNTEREN JAN VAN

IPC: G05B19/045

公开(公告)号：IE20010248A1

公开(公告)日：2002-07-24

申请号：IE20010248

申请日：2001-03-14

Applicant: IBM

Inventor： LUNTEREN JAN VAN

IPC: G06F17/30 ,  H04L12/56

Abstract: The invention relates to a system in which given search keys are evaluated, segment by segment, to search through tree-structured tables for finding an output information corresponding to the longest matching prefix. For at least one of the segments, only selected bits of the search key segment are used as index for accessing an associated table where test values are stored which are to be compared to the respective search key segment. The bits to be selected are determined by an index mask, reflecting the distribution of the valid test values in the table entries (and valid search key segment values). This allows table compression for minimizing storage requirements and search time. A procedure is disclosed for generating an optimum index mask in response to the set of valid test values.