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    Progammable two table indexed finite state machine
    1.
    发明专利
    Progammable two table indexed finite state machine 未知

    公开(公告)号：GB2461648A

    公开(公告)日：2010-01-13

    申请号：GB0913415

    申请日：2009-08-03

    Applicant: IBM

    Inventor： SCHLIPF THOMAS ,  FRITZ ROLF ,  SMITH CHRISTOPHER S ,  MAYER ULRICH ,  LUNTEREN JAN VAN

    IPC: G05B19/045

    Abstract: A system stores an input compare vector in an input compare vector table. The system also stores an output vector, a next state value and a next state start address in an output vector, next state, next state address table. Each comparator compares each input compare vector from the input compare vector table and an external input vector, and outputs a selection signal to a multiplexer. The multiplexer associates the selection signals with an offset value, and provides the offset value to adder logic. The adder logic adds the offset value and an address from a current state start address register. A result of the addition is used as an address to access a row in the output vector, next state, next state address table. The accessed row has an output vector, a next state value and a next state start address corresponding to a current state and the external input vector.

    Multiprocessor system with synchronization of error recovery to prevent errors spreading
    2.
    发明专利
    Multiprocessor system with synchronization of error recovery to prevent errors spreading 未知

    公开(公告)号：GB2456403A

    公开(公告)日：2009-07-22

    申请号：GB0822313

    申请日：2008-12-08

    Applicant: IBM

    Inventor： KOENIG ANDREAS ,  SCHLIPF THOMAS ,  KLEIN MATTHIAS ,  WALZ MANFRED ,  FRITZ ROLF

    IPC: G06F11/07

    Abstract: A method of operating self-testing logic in a tree-like multi-chip processor cluster which generates an infrastructure signal 430, such as a clockstop or tracestop signal, used for error management and recovery. The operation intercepts 440 the infrastructure signal of a processor of the cluster then extracts error information from the infrastructure signal. Using the error information a pre-defined inter-chip error synchronisation scheme is selected 450 including clock-stop and/or trace-stop information for a respective one of the processors of the cluster. Notification signals are distributed 490 to chips of the cluster using dedicated wires or a low-level standard interface for chip-to-chip communication to prepare and execute error related internal operations for chips. On receipt of one of the notification signals a chip performs at least one of (i) performing a trace-stop command or (ii) performing a clock-stop command 495 on a respective one of the chips as derived from the synchronisation scheme. The synchronisation scheme may comprise a configurable delay adjustable according to the location of the failure within the chip.

    Error handling using domains
    5.
    发明专利
    Error handling using domains 未知

    公开(公告)号：GB2455010A

    公开(公告)日：2009-06-03

    申请号：GB0822774

    申请日：2008-12-15

    Applicant: IBM

    Inventor： KLEIN MATTHIAS ,  KOENIG ANDREAS ,  FRITZ ROLF

    IPC: G06F11/07

    Abstract: A method/apparatus for controlling an error handling procedure in a digital circuit with control logic comprises a plurality of control logic circuits 20 grouped into a number of error handling domains 26, 28. Each error handling domain 26, 28 is associated with a predetermined data flow of the digital circuit. The digital circuit comprises an extended error reporting unit 24 for receiving an indication of an error 30 in the control logic. The extended error reporting unit 24 includes a mask system for mapping the single errors onto error handling procedures. The digital circuit comprises an error handling unit 22 for performing the operations of the error handling procedure on the according component of the digital circuit. The control logic circuits could be implemented using finite state machines. This error handling system enables all errors to be handled using well-tested error handling procedures instead of being handled locally.

    Programmable communicating finite state machines with mealy communication behaviour
    8.
    发明专利
    Programmable communicating finite state machines with mealy communication behaviour 未知

    公开(公告)号：GB2461649A

    公开(公告)日：2010-01-13

    申请号：GB0913420

    申请日：2009-08-03

    Applicant: IBM

    Inventor： SCHLIPF THOMAS ,  FRITZ ROLF ,  SMITH CHRISTOPHER S ,  MAYER ULRICH ,  LUNTEREN JAN VAN

    IPC: G05B19/045

    Abstract: Preventing a communication loop in communicating finite state machines by providing two tables, an output next state (OTNS) table and a communication output (COUT) table. The OTNS table is divided into two array data structures, an input compare vector (ICVT1) and an output next state next address table (ONNT). The COUT table is divided into two array data structures, an input compare vector (ICVT2) and a communication output table (COMCONT). Input compare vectors in the ICVT1 are retrieved and fed into comparators. The comparators compare the retrieved input compare vectors with an input signal. When a match is found, a corresponding comparator sets a corresponding selection signal to a pre-determined value to generate an offset value through a multiplexer. An adder adds the offset value and a value stored in a current state start address (CSSA) register, and generates an adding result. The adding result is used as an address to access a row in the ONNT. There is state transition information in that row of the ONNT.

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